PIC18F97J60-I/PF Microchip Technology, PIC18F97J60-I/PF Datasheet - Page 331

• Manufacturer Part Number: PIC18F97J60-I/PF
• Description: IC PIC MCU FLASH 65KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F97J60-I/PF

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Operating Supply Voltage: 2.35 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Package: 100TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 41.667 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100DM163024 - BOARD DEMO PICDEM.NET 2
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

21.2
The ADCON2 register allows the user to select an
acquisition time that occurs each time the GO/DONE
bit is set.
When the GO/DONE bit is set, sampling is stopped and
a conversion begins. The user is responsible for ensur-
ing the required acquisition time has passed between
selecting the desired input channel and setting the
GO/DONE bit. This occurs when the ACQT2:ACQT0
bits (ADCON2<5:3>) remain in their Reset state (‘000’)
and is compatible with devices that do not offer
programmable acquisition times.
If desired, the ACQT bits can be set to select a
programmable acquisition time for the A/D module.
When the GO/DONE bit is set, the A/D module continues
to sample the input for the selected acquisition time, then
automatically begins a conversion. Since the acquisition
time is programmed, there may be no need to wait for an
acquisition time between selecting a channel and setting
the GO/DONE bit.
In either case, when the conversion is completed, the
GO/DONE bit is cleared, the ADIF flag is set and the
A/D begins sampling the currently selected channel
again. If an acquisition time is programmed, there is
nothing to indicate if the acquisition time has ended or
if the conversion has begun.
21.3
The A/D conversion time per bit is defined as T
A/D conversion requires 11 T
The source of the A/D conversion clock is software
selectable.
There are seven possible options for T
• 2 T
• 4 T
• 8 T
• 16 T
• 32 T
• 64 T
• Internal RC Oscillator
For correct A/D conversions, the A/D conversion clock
(T
the minimum T
Characteristics”, A/D parameter 130 in Table 27-27
for more information.
© 2006 Microchip Technology Inc.
AD
) must be as short as possible but greater than
OSC
OSC
OSC
OSC
OSC
OSC
Selecting and Configuring
Automatic Acquisition Time
Selecting the A/D Conversion
Clock
AD
. See Section 27.0 “Electrical
AD
per 10-bit conversion.
AD
:
AD
. The
Preliminary
PIC18F97J60 FAMILY
Table 21-1 shows the resultant T
the device operating frequencies and the A/D clock
source selected.
TABLE 21-1:
21.4
The ADCON1, TRISA, TRISF and TRISH registers
control the operation of the A/D port pins. The port pins
needed as analog inputs must have their correspond-
ing TRIS bits set (input). If the TRIS bit is cleared
(output), the digital output level (V
converted.
The A/D operation is independent of the state of the
CHS3:CHS0 bits and the TRIS bits.
Note 1:
Note 1: When reading the PORT register, all pins
Operation
16 T
32 T
64 T
2 T
4 T
8 T
AD Clock Source (T
RC
2:
OSC
OSC
OSC
2: Analog levels on any pin defined as a
Configuring Analog Port Pins
OSC
OSC
OSC
(2)
The RC source has a typical T
4 ms.
See parameter 130 in Table 27-27 for A/D
RC clock specifications.
configured as analog input channels will
read as cleared (a low level). Pins config-
ured as digital inputs will convert an
analog input. Analog levels on a digitally
configured
converted.
digital input may cause the digital input
buffer to consume current out of the
device’s specification limits.
T
FREQUENCIES
ADCS2:ADCS0
AD
vs. DEVICE OPERATING
000
100
001
101
010
110
x11
input
AD
)
AD
will
DS39762B-page 329
OH
times derived from
be
or V
Frequency
11.43 MHz
22.86 MHz
41.67 MHz
41.67 MHz
Maximum
1.00 MHz
2.68 MHz
5.71 MHz
Device
AD
accurately
OL
time of
) will be
(1)