PIC18F97J60-I/PF Microchip Technology, PIC18F97J60-I/PF Datasheet - Page 155

• Manufacturer Part Number: PIC18F97J60-I/PF
• Description: IC PIC MCU FLASH 65KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F97J60-I/PF

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Operating Supply Voltage: 2.35 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Package: 100TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 41.667 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100DM163024 - BOARD DEMO PICDEM.NET 2
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TABLE 10-15: PORTG FUNCTIONS
© 2006 Microchip Technology Inc.
RG0/ECCP3/
P3A
RG1/TX2/
CK2
RG2/RX2/
DT2
RG3/CCP4/
P3D
RG4/CCP5/
P1D
RG5
RG6
RG7
Legend:
Note 1:
Pin Name
(1)
(1)
(1)
(1)
(2)
(2)
(2)
2:
O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Implemented on 80-pin and 100-pin devices only.
Implemented on 100-pin devices only.
ECCP3
Function
CCP4
RG0
RG1
RG2
RG3
RG5
RG6
RG7
P3A
TX2
CK2
RX2
DT2
P3D
CCP5
RG4
P1D
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(2)
(2)
(2)
(1)
(1)
Setting
TRIS
0
1
0
1
0
0
1
1
1
1
0
1
1
1
1
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
1
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Type
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
I/O
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
Preliminary
LATG<0> data output.
PORTG<0> data input.
ECCP3 compare and PWM output; takes priority over port data.
ECCP3 capture input.
ECCP3 Enhanced PWM output, channel A; takes priority over port and
PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
LATG<1> data output.
PORTG<1> data input.
Synchronous serial data output (EUSART2 module); takes priority over
port data.
Synchronous serial data input (EUSART2 module). User must configure
as an input.
Synchronous serial clock input (EUSART2 module).
LATG<2> data output.
PORTG<2> data input.
Asynchronous serial receive data input (EUSART2 module).
Synchronous serial data output (EUSART2 module); takes priority over
port data.
Synchronous serial data input (EUSART2 module). User must configure
as an input.
LATG<3> data output.
PORTG<3> data input.
CCP4 compare output and PWM output; takes priority over port data.
CCP4 capture input.
ECCP3 Enhanced PWM output, channel D; takes priority over port and
PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
LATG<4> data output.
PORTG<4> data input.
CCP5 compare output and PWM output; takes priority over port data.
CCP5 capture input.
ECCP1 Enhanced PWM output, channel D; takes priority over port and
PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
LATG<0> data output.
PORTG<0> data input.
LATG<0> data output.
PORTG<0> data input.
LATG<0> data output.
PORTG<0> data input.
PIC18F97J60 FAMILY
Description
DS39762B-page 153