PIC18F97J60-I/PF Microchip Technology, PIC18F97J60-I/PF Datasheet - Page 233

• Manufacturer Part Number: PIC18F97J60-I/PF
• Description: IC PIC MCU FLASH 65KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F97J60-I/PF

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Operating Supply Voltage: 2.35 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Package: 100TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 41.667 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100DM163024 - BOARD DEMO PICDEM.NET 2
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

REGISTER 18-18: MABBIPG: MAC BACK-TO-BACK INTER-PACKET GAP REGISTER
18.4.6
Depending on the application, bits in three of the PHY
module’s registers may also require configuration.
The PDPXMD bit (PHCON1<8>) controls the PHY
half/full-duplex configuration. The application must
program the bit properly, along with the FULDPX bit
(MACON3<0>).
The HDLDIS bit (PHCON2<8>) disables automatic
loopback of data. For proper operation, always set both
HDLDIS and RXAPDIS (PHCON2<4>).
The PHY register, PHLCON (Register 18-13), controls
the outputs of LEDA and LEDB. If an application
requires a LED configuration other than the default,
alter this register to match the new requirements. The
settings
Section 18.1.2 “LED Configuration”.
© 2006 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6-0
U-0
—
for
PHY INITIALIZATION SETTINGS
LED
Unimplemented: Read as ‘0’
BBIPG6:BBIPG0: Back-to-Back Inter-Packet Gap Delay Time bits
When FULDPX (MACON3<0>) = 1:
Nibble time offset delay between the end of one transmission and the beginning of the next in a
back-to-back sequence. The register value should be programmed to the desired period in nibble
times minus 3. The recommended setting is 15h which represents the minimum IEEE specified
Inter-Packet Gap (IPG) of 9.6 s.
When FULDPX (MACON3<0>) = 0:
Nibble time offset delay between the end of one transmission and the beginning of the next in a
back-to-back sequence. The register value should be programmed to the desired period in nibble
times minus 6. The recommended setting is 12h which represents the minimum IEEE specified
Inter-Packet Gap (IPG) of 9.6 s.
BBIPG6
R/W-0
operation
W = Writable bit
‘1’ = Bit is set
BBIPG5
are
R/W-0
discussed
BBIPG4
R/W-0
Preliminary
in
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PIC18F97J60 FAMILY
BBIPG3
R/W-0
18.4.7
There may be circumstances during which the Ethernet
module is not needed for prolonged periods. For exam-
ple, in situations where the application only needs to
transmit or receive Ethernet packets on the occurrence
of a particular event. In these cases, the module can be
selectively powered down.
To selectively disable the module:
1.
2.
3.
4.
Turn off packet reception by clearing the RXEN
bit.
Wait for any in-progress packets to finish being
received
(ESTAT<2>). This bit should be clear before
proceeding.
Wait for any current transmissions to end by
confirming that the TXRTS bit (ECON1<3>) is
clear.
Clear the ETHEN bit. This removes power and
clock sources from the module, and makes the
PHY registers inaccessible. The PHYRDY bit is
also cleared automatically.
DISABLING THE ETHERNET
MODULE
BBIPG2
R/W-0
by
polling
x = Bit is unknown
BBIPG1
R/W-0
the
DS39762B-page 231
RXBUSY
BBIPG0
R/W-0
bit 0
bit