PIC18F97J60-I/PF Microchip Technology, PIC18F97J60-I/PF Datasheet - Page 143

IC PIC MCU FLASH 65KX16 100TQFP

PIC18F97J60-I/PF

Manufacturer Part Number
PIC18F97J60-I/PF
Description
IC PIC MCU FLASH 65KX16 100TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18F97J60-I/PF

Program Memory Type
FLASH
Program Memory Size
128KB (64K x 16)
Package / Case
100-TQFP, 100-VQFP
Core Processor
PIC
Core Size
8-Bit
Speed
41.667MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
70
Ram Size
3808 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3808 B
Interface Type
Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
Maximum Clock Frequency
41.667 MHz
Number Of Programmable I/os
70
Number Of Timers
5
Operating Supply Voltage
2.35 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
Package
100TQFP
Device Core
PIC
Family Name
PIC18
Maximum Speed
41.667 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162064 - HEADER INTFC MPLABICD2 64/80/100DM163024 - BOARD DEMO PICDEM.NET 2
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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10.4
PORTC is an 8-bit wide, bidirectional port; it is fully
implemented on all devices. The corresponding Data
Direction register is TRISC. Setting a TRISC bit (= 1)
will make the corresponding PORTC pin an input (i.e.,
put
high-impedance mode). Clearing a TRISC bit (= 0) will
make the corresponding PORTC pin an output (i.e., put
the contents of the output latch on the selected pin).
Only PORTC pins, RC2 through RC7, are digital only
pins and can tolerate input voltages up to 5.5V.
The Output Latch register (LATC) is also memory
mapped. Read-modify-write operations on the LATC
register read and write the latched output value for
PORTC.
PORTC is multiplexed with several peripheral functions
(Table 10-7). The pins have Schmitt Trigger input
buffers. RC1 is normally configured by Configuration
bit, CCP2MX, as the default peripheral pin for the
ECCP2 module and Enhanced PWM output P2A
(default state, CCP2MX = 1).
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an output,
while other peripherals override the TRIS bit to make a
pin an input. The user should refer to the corresponding
peripheral section for the correct TRIS bit settings.
© 2006 Microchip Technology Inc.
the
PORTC, TRISC and
LATC Registers
corresponding
output
driver
in
Preliminary
a
PIC18F97J60 FAMILY
The contents of the TRISC register are affected by
peripheral overrides. Reading TRISC always returns
the current contents, even though a peripheral device
may be overriding one or more of the pins.
EXAMPLE 10-3:
CLRF
CLRF
MOVLW
MOVWF
Note:
PORTC
LATC
0CFh
TRISC
These pins are configured as digital inputs
on any device Reset.
; Initialize PORTC by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RC<3:0> as inputs
; RC<5:4> as outputs
; RC<7:6> as inputs
INITIALIZING PORTC
DS39762B-page 141

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