PIC18F97J60-I/PF Microchip Technology, PIC18F97J60-I/PF Datasheet - Page 139

IC PIC MCU FLASH 65KX16 100TQFP

PIC18F97J60-I/PF

Manufacturer Part Number
PIC18F97J60-I/PF
Description
IC PIC MCU FLASH 65KX16 100TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18F97J60-I/PF

Program Memory Type
FLASH
Program Memory Size
128KB (64K x 16)
Package / Case
100-TQFP, 100-VQFP
Core Processor
PIC
Core Size
8-Bit
Speed
41.667MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
70
Ram Size
3808 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3808 B
Interface Type
Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
Maximum Clock Frequency
41.667 MHz
Number Of Programmable I/os
70
Number Of Timers
5
Operating Supply Voltage
2.35 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
Package
100TQFP
Device Core
PIC
Family Name
PIC18
Maximum Speed
41.667 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162064 - HEADER INTFC MPLABICD2 64/80/100DM163024 - BOARD DEMO PICDEM.NET 2
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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TABLE 10-3:
TABLE 10-4:
© 2006 Microchip Technology Inc.
PORTA
LATA
TRISA
ADCON1
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA.
Note 1:
RA0/LEDA/AN0
RA1/LEDB/AN1
RA2/AN2/V
RA3/AN3/V
RA4/T0CKI
RA5/AN4
Legend:
Pin Name
Name
REF
REF
Implemented in 80-pin and 100-pin devices only.
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
-
+
RJPU
RDPU
Bit 7
Function
PORTA FUNCTIONS
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
V
T0CKI
LEDA
LEDB
V
RA0
AN0
RA1
AN1
RA2
AN2
RA3
AN3
RA4
RA5
AN4
REF
REF
(1)
+
-
REPU
Bit 6
Setting
TRIS
0
1
0
1
0
1
0
1
0
1
1
1
0
1
1
1
0
1
x
0
1
1
TRISA5
VCFG1
LATA5
Bit 5
RA5
I/O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Type
ANA
ANA
ANA
ANA
ANA
ANA
ANA
DIG
TTL
DIG
DIG
TTL
DIG
DIG
TTL
DIG
TTL
DIG
DIG
TTL
I/O
ST
ST
TRISA4
VCFG0
LATA4
Preliminary
Bit 4
RA4
LATA<0> data output; not affected by analog input.
PORTA<0> data input; disabled when analog input enabled.
Ethernet LEDA output; takes priority over digital data.
A/D input channel 0. Default input configuration on POR; does not
affect digital output.
LATA<1> data output; not affected by analog input.
PORTA<1> data input; disabled when analog input enabled.
Ethernet LEDB output; takes priority over digital data.
A/D input channel 1. Default input configuration on POR; does not
affect digital output.
LATA<2> data output; not affected by analog input. Disabled when
CV
PORTA<2> data input. Disabled when analog functions enabled;
disabled when CV
A/D input channel 2 and comparator C2+ input. Default input
configuration on POR; not affected by analog output.
A/D and comparator low reference voltage input.
LATA<3> data output; not affected by analog input.
PORTA<3> data input; disabled when analog input enabled.
A/D input channel 3. Default input configuration on POR.
A/D high reference voltage input.
LATA<4> data output.
PORTA<4> data input; default configuration on POR.
Timer0 clock input.
LATA<5> data output; not affected by analog input.
PORTA<5> data input; disabled when analog input enabled.
A/D input channel 4. Default configuration on POR.
REF
TRISA3
PCFG3
PIC18F97J60 FAMILY
output enabled.
LATA3
Bit 3
RA3
REF
TRISA2
PCFG2
LATA2
Bit 2
RA2
output enabled.
Description
TRISA1
PCFG1
LATA1
Bit 1
RA1
TRISA0
PCFG0
LATA0
Bit 0
RA0
DS39762B-page 137
Values on
Reset
Page:
62
62
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60

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