PIC18F97J60-I/PF Microchip Technology, PIC18F97J60-I/PF Datasheet - Page 226

• Manufacturer Part Number: PIC18F97J60-I/PF
• Description: IC PIC MCU FLASH 65KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F97J60-I/PF

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Operating Supply Voltage: 2.35 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Package: 100TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 41.667 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100DM163024 - BOARD DEMO PICDEM.NET 2
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F97J60 FAMILY
18.3
The Ethernet module can generate multiple interrupt
conditions. To accommodate all of these sources, the
module has its own interrupt logic structure, similar to
that of the microcontroller. Separate sets of registers
are used to enable and flag different interrupt
conditions.
The EIE register contains the individual interrupt
enable bits for each source, while the EIR register con-
tains the corresponding interrupt flag bits. When an
interrupt occurs, the interrupt flag is set. If the interrupt
is enabled in the EIE register, and the corresponding
ETHIE global interrupt enable bit is set, the micro-
controller’s master Ethernet Interrupt Flag (ETHIF) is
set, as appropriate (see Figure 18-6).
FIGURE 18-6:
DS39762B-page 224
PLNKIF
PLNKIE
Ethernet Interrupts
ETHERNET MODULE INTERRUPT LOGIC
PGEIE
PGIF
LINKIF
RXERIF
RXERIE
TXERIF
TXERIE
DMAIE
LINKIE
PKTIE
DMAIF
PKTIF
TXIF
TXIE
Preliminary
18.3.1
The four registers associated with the control interrupts
are shown in Register 18-14 through Register 18-17.
Note:
ETHIE
Except for the LINKIF interrupt flag,
interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the associ-
ated global enable bit. User software
should ensure the appropriate interrupt
flag bits are clear prior to enabling an
interrupt. This feature allows for software
polling.
CONTROL INTERRUPT (ETHIE)
© 2006 Microchip Technology Inc.
Set ETHIF