PIC18F97J60-I/PF Microchip Technology, PIC18F97J60-I/PF Datasheet - Page 87

• Manufacturer Part Number: PIC18F97J60-I/PF
• Description: IC PIC MCU FLASH 65KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F97J60-I/PF

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Operating Supply Voltage: 2.35 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Package: 100TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 41.667 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100DM163024 - BOARD DEMO PICDEM.NET 2
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TABLE 5-5:
© 2006 Microchip Technology Inc.
ESTAT
EIE
EDMACSH
EDMACSL
EDMADSTH
EDMADSTL
EDMANDH
EDMANDL
EDMASTH
EDMASTL
ERXWRPTH
ERXWRPTL
ERXRDPTH
ERXRDPTL
ERXNDH
ERXNDL
ERXSTH
ERXSTL
ETXNDH
ETXNDL
ETXSTH
ETXSTL
EWRPTH
EWRPTL
EPKTCNT
ERXFCON
EPMOH
EPMOL
EPMCSH
EPMCSL
EPMM7
EPMM6
EPMM5
EPMM4
EPMM3
EPMM2
EPMM1
EPMM0
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’, q = value depends on condition, r = reserved bit, do not modify. Shaded cells
Note 1:
File Name
2:
3:
4:
5:
6:
7:
8:
9:
are unimplemented, read as ‘0’.
Bit 7 and bit 6 are cleared by user software or by a POR.
Bit 21 of the PC is only available in Serial Programming modes.
Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
Alternate names and definitions for these bits when the MSSP module is operating in I
These bits and/or registers are only available in 100-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values shown
apply only to 100-pin devices.
These bits and/or registers are only available in 80-pin and 100-pin devices; in 64-pin devices, they are unimplemented and read as ‘0’. Reset
values are shown for 100-pin devices.
In Microcontroller mode, the bits in this register are unwritable and read as ‘0’.
PLLEN is only available when either ECPLL or HSPLL Oscillator mode is selected; otherwise, read as ‘0’.
Implemented in 100-pin devices in Microcontroller mode only.
DMA Checksum Register High Byte
DMA Checksum Register Low Byte
DMA Destination Register Low Byte
DMA End Register Low Byte
DMA Start Register Low Byte
Receive Buffer Write Pointer Low Byte
Receive Buffer Read Pointer Low Byte
Receive End Register Low Byte
Receive Start Register Low Byte
Transmit End Register Low Byte
Transmit Start Register Low Byte
Buffer Write Pointer Low Byte
Ethernet Packet Count Register
Pattern Match Offset Register Low Byte
Pattern Match Checksum Register High Byte
Pattern Match Checksum Register Low Byte
Pattern Match Mask Register Byte 7
Pattern Match Mask Register Byte 6
Pattern Match Mask Register Byte 5
Pattern Match Mask Register Byte 4
Pattern Match Mask Register Byte 3
Pattern Match Mask Register Byte 2
Pattern Match Mask Register Byte 1
Pattern Match Mask Register Byte 0
UCEN
Bit 7
—
—
—
—
—
—
—
—
—
—
—
—
—
REGISTER FILE SUMMARY (PIC18F97J60 FAMILY) (CONTINUED)
ANDOR
BUFER
PKTIE
Bit 6
—
—
—
—
—
—
—
—
—
—
—
CRCEN
DMAIE
Bit 5
—
—
—
—
—
—
—
—
—
—
—
—
DMA Destination Register High Byte
DMA End Register High Byte
DMA Start Register High Byte
Receive Buffer Write Pointer High Byte
Receive Buffer Read Pointer High Byte
Receive End Register High Byte
Receive Start Register High Byte
Transmit End Register High Byte
Transmit Start Register High Byte
Buffer Write Pointer High Byte
Pattern Match Offset Register High Byte
LINKIE
PMEN
Bit 4
r
Preliminary
MPEN
Bit 3
TXIE
—
PIC18F97J60 FAMILY
RXBUSY
HTEN
Bit 2
—
2
C™ Slave mode.
TXABRT
TXERIE
MCEN
Bit 1
PHYRDY
RXERIE
BCEN
Bit 0
-0-0 -000
-000 0-00
0000 0000
0000 0000
---0 0000
0000 0000
---0 0000
0000 0000
---0 0000
0000 0000
---0 0000
0000 0000
---0 0101
1111 1010
---1 1111
1111 1111
---0 0101
1111 1010
---0 0000
0000 0000
---0 0000
0000 0000
---0 0000
0000 0000
0000 0000
1010 0001
---0 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
POR, BOR
Values on
DS39762B-page 85
Details on
63, 213
63, 225
63, 250
63, 250
63, 250
63, 250
63, 250
63, 250
63, 250
63, 250
63, 210
63, 210
63, 210
63, 210
63, 210
63, 210
63, 210
63, 210
64, 209
64, 209
64, 237
64, 245
64, 248
64, 248
64, 248
64, 248
64, 248
64, 248
64, 248
64, 248
64, 248
64, 248
64, 248
64, 248
64, 211
64, 211
64, 211
64, 211
Page: