PIC18F97J60-I/PF Microchip Technology, PIC18F97J60-I/PF Datasheet - Page 280
PIC18F97J60-I/PF
Manufacturer Part Number
PIC18F97J60-I/PF
Description
IC PIC MCU FLASH 65KX16 100TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F66J65-IPT.pdf
(8 pages)
3.PIC18F66J65-IPT.pdf
(480 pages)
4.PIC18F66J65-IPT.pdf
(4 pages)
5.PIC18F66J65-IPT.pdf
(10 pages)
6.PIC18F96J60-IPT.pdf
(24 pages)
7.PIC18F97J60-IPF.pdf
(472 pages)
Specifications of PIC18F97J60-I/PF
Program Memory Type
FLASH
Program Memory Size
128KB (64K x 16)
Package / Case
100-TQFP, 100-VQFP
Core Processor
PIC
Core Size
8-Bit
Speed
41.667MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
70
Ram Size
3808 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3808 B
Interface Type
Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
Maximum Clock Frequency
41.667 MHz
Number Of Programmable I/os
70
Number Of Timers
5
Operating Supply Voltage
2.35 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
Package
100TQFP
Device Core
PIC
Family Name
PIC18
Maximum Speed
41.667 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162064 - HEADER INTFC MPLABICD2 64/80/100DM163024 - BOARD DEMO PICDEM.NET 2
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F97J60-I/PF
Manufacturer:
MICRRCHIP
Quantity:
1 800
Company:
Part Number:
PIC18F97J60-I/PF
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F97J60-I/PF
Manufacturer:
MICROCHI
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PIC18F66J65-IPT PDF datasheet #2
- PIC18F66J65-IPT PDF datasheet #3
- PIC18F66J65-IPT PDF datasheet #4
- PIC18F66J65-IPT PDF datasheet #5
- PIC18F96J60-IPT PDF datasheet #6
- PIC18F97J60-IPF PDF datasheet #7
- Current page: 280 of 472
- Download datasheet (8Mb)
PIC18F97J60 FAMILY
19.4.4.5
When the CKP bit is cleared, the SCLx output is forced
to ‘0’. However, clearing the CKP bit will not assert the
SCLx output low until the SCLx output is already sam-
pled low. Therefore, the CKP bit will not assert the
SCLx line until an external I
FIGURE 19-14:
DS39762B-page 278
SDAx
SCLx
CKP
WR
SSPxCON1
Clock Synchronization and
the CKP bit
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CLOCK SYNCHRONIZATION TIMING
2
C master device has
DX
Master device
asserts clock
Preliminary
already asserted the SCLx line. The SCLx output will
remain low until the CKP bit is set and all other
devices on the I
ensures that a write to the CKP bit will not violate the
minimum high time requirement for SCLx (see
Figure 19-14).
Master device
deasserts clock
2
C bus have deasserted SCLx. This
© 2006 Microchip Technology Inc.
DX – 1
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