PIC18F97J60-I/PF Microchip Technology, PIC18F97J60-I/PF Datasheet - Page 57

• Manufacturer Part Number: PIC18F97J60-I/PF
• Description: IC PIC MCU FLASH 65KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F97J60-I/PF

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Operating Supply Voltage: 2.35 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Package: 100TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 41.667 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100DM163024 - BOARD DEMO PICDEM.NET 2
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.2
The MCLR pin provides a method for triggering a hard
external Reset of the device. A Reset is generated by
holding the pin low. PIC18 extended microcontroller
devices have a noise filter in the MCLR Reset path
which detects and ignores small pulses.
The MCLR pin is not driven low by any internal Resets,
including the WDT.
4.3
A Power-on Reset condition is generated on-chip
whenever V
allows the device to start in the initialized state when
V
To take advantage of the POR circuitry, tie the MCLR
pin through a resistor (1 k
eliminate external RC components usually needed to
create a Power-on Reset delay. A minimum rise rate for
V
time, see Figure 4-2.
When the device starts normal operation (i.e., exits the
Reset
(voltage, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
POR events are captured by the POR bit (RCON<1>).
The state of the bit is set to ‘0’ whenever a Power-on
Reset occurs; it does not change for any other Reset
event. POR is not reset to ‘1’ by any hardware event.
To capture multiple events, the user manually resets
the bit to ‘1’ in software following any Power-on Reset.
4.4
The PIC18F97J60 family of devices incorporates a
simple BOR function when the internal regulator is
enabled (ENVREG pin is tied to V
below V
T
may or may not occur if V
than T
until V
Once a BOR has occurred, the Power-up Timer will
keep the chip in Reset for T
V
running, the chip will go back into a Brown-out Reset
and the Power-up Timer will be initialized. Once V
rises above V
additional time delay.
© 2006 Microchip Technology Inc.
DD
DD
BOR
DD
is adequate for operation.
drops below V
is specified (parameter D004). For a slow rise
(parameter 35), will reset the device. A Reset
DD
BOR
BOR
condition),
Master Clear (MCLR)
Power-on Reset (POR)
Brown-out Reset (BOR)
rises above V
. The chip will remain in Brown-out Reset
DD
(parameter D005), for greater than time
BOR
rises above a certain threshold. This
, the Power-up Timer will execute the
BOR
device
BOR
while the Power-up Timer is
DD
.
to 10 k ) to V
falls below V
PWRT
operating
DD
). Any drop of V
(parameter 33). If
DD
BOR
parameters
. This will
for less
Preliminary
DD
DD
PIC18F97J60 FAMILY
FIGURE 4-2:
4.4.1
The BOR bit always resets to ‘0’ on any Brown-out
Reset or Power-on Reset event. This makes it difficult
to determine if a Brown-out Reset event has occurred
just by reading the state of BOR alone. A more reliable
method is to simultaneously check the state of both
POR and BOR. This assumes that the POR bit is reset
to ‘1’ in software immediately after any Power-on Reset
event. If BOR is ‘0’ while POR is ‘1’, it can be reliably
assumed that a Brown-out Reset event has occurred.
If the voltage regulator is disabled, Brown-out Reset
functionality is disabled. In this case, the BOR bit
cannot be used to determine a Brown-out Reset event.
The BOR bit is still cleared by a Power-on Reset event.
4.5
The Configuration Mismatch (CM) Reset is designed to
detect and attempt to recover from random, memory
corrupting
Discharge (ESD) events which can cause widespread
single-bit changes throughout the device and result in
catastrophic failure.
In PIC18FXXJ Flash devices, the device Configuration
registers (located in the configuration memory space)
are continuously monitored during operation by com-
paring their values to complimentary shadow registers.
If a mismatch is detected between the two sets of
registers, a CM Reset automatically occurs. These
events are captured by the CM bit (RCON<5>). The
state of the bit is set to ‘0’ whenever a CM event occurs;
it does not change for any other Reset event.
Note 1: External Power-on Reset circuit is required
V
DD
2: R < 40 k is recommended to make sure that
3: R1
Configuration Mismatch (CM)
D
(1)
DETECTING BOR
only if the V
The diode D helps discharge the capacitor
quickly when V
the voltage drop across R does not violate
the device’s electrical specification.
MCLR from external capacitor C in the event
of MCLR/V
Electrostatic Discharge (ESD), or Electrical
Overstress (EOS).
events.
V
DD
R
C
1 k
(2)
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW V
will limit any current flowing into
These
DD
PP
R1
DD
(3)
power-up slope is too slow.
pin breakdown, due to
powers down.
MCLR
PIC18FXXJ6X
include
DD
POWER-UP)
DS39762B-page 55
Electrostatic