PIC18F97J60-I/PF Microchip Technology, PIC18F97J60-I/PF Datasheet - Page 236

• Manufacturer Part Number: PIC18F97J60-I/PF
• Description: IC PIC MCU FLASH 65KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F97J60-I/PF

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Operating Supply Voltage: 2.35 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Package: 100TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 41.667 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100DM163024 - BOARD DEMO PICDEM.NET 2
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F97J60 FAMILY
18.5.2
The Ethernet module’s MAC will automatically
generate the preamble and Start-of-Frame (SOF)
delimiter fields when transmitting. Additionally, the
MAC can generate any padding (if needed) and the
CRC if configured to do so. The application must
generate and write all other frame fields into the buffer
memory for transmission.
FIGURE 18-8:
DS39762B-page 234
bit 7
bit 7-4
bit 3
bit 2
bit 1
bit 0
—
TRANSMITTING PACKETS
Unimplemented: Read as ‘0’
PHUGEEN: Per-Packet Huge Frame Enable bit
When POVERRIDE = 1:
1 = The packet will be transmitted in whole
0 = The MAC will transmit up to the number of bytes specified by the MAMXFL registers. If the packet
When POVERRIDE = 0:
This bit is ignored.
PPADN: Per-Packet Padding Enable bit
When POVERRIDE = 1:
1 = The packet will be zero-padded to 60 bytes if it is less than 60 bytes
0 = The packet will be transmitted without adding any padding bytes
When POVERRIDE = 0:
This bit is ignored.
PCRCEN: Per-Packet CRC Enable bit
When POVERRIDE = 1:
1 = A valid CRC will be calculated and attached to the frame
0 = No CRC will be appended. The last 4 bytes of the frame will be checked for validity as a CRC.
When POVERRIDE = 0:
This bit is ignored.
POVERRIDE: Per-Packet Override bit
1 = The values of PCRCEN, PPADN and PHUGEEN will override the configuration defined by
0 = The values in MACON3 will be used to determine how the packet will be transmitted
is larger than the bytes specified, it will be aborted after the MAMXFL registers specification is
reached.
MACON3
—
FORMAT FOR PER-PACKET CONTROL BYTES
—
—
Preliminary
PHUGEEN
In addition, the Ethernet module requires a single
per-packet control byte to precede the packet for trans-
mission. The control byte is organized as shown in
Figure 18-8. Before transmitting packets, the MAC
registers, which alter the transmission characteristics,
should be initialized as documented in Section 18.4
“Module Initialization”.
PPADN
© 2006 Microchip Technology Inc.
PCRCEN
POVERRIDE
bit 0