PIC18F97J60-I/PF Microchip Technology, PIC18F97J60-I/PF Datasheet - Page 271
![IC PIC MCU FLASH 65KX16 100TQFP](/photos/12/13/121330/c04-100-tqfp_sml.jpg)
PIC18F97J60-I/PF
Manufacturer Part Number
PIC18F97J60-I/PF
Description
IC PIC MCU FLASH 65KX16 100TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F66J65-IPT.pdf
(8 pages)
3.PIC18F66J65-IPT.pdf
(480 pages)
4.PIC18F66J65-IPT.pdf
(4 pages)
5.PIC18F66J65-IPT.pdf
(10 pages)
6.PIC18F96J60-IPT.pdf
(24 pages)
7.PIC18F97J60-IPF.pdf
(472 pages)
Specifications of PIC18F97J60-I/PF
Program Memory Type
FLASH
Program Memory Size
128KB (64K x 16)
Package / Case
100-TQFP, 100-VQFP
Core Processor
PIC
Core Size
8-Bit
Speed
41.667MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
70
Ram Size
3808 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3808 B
Interface Type
Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
Maximum Clock Frequency
41.667 MHz
Number Of Programmable I/os
70
Number Of Timers
5
Operating Supply Voltage
2.35 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
Package
100TQFP
Device Core
PIC
Family Name
PIC18
Maximum Speed
41.667 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162064 - HEADER INTFC MPLABICD2 64/80/100DM163024 - BOARD DEMO PICDEM.NET 2
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Price
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- PIC16F616T-ISL PDF datasheet
- PIC18F66J65-IPT PDF datasheet #2
- PIC18F66J65-IPT PDF datasheet #3
- PIC18F66J65-IPT PDF datasheet #4
- PIC18F66J65-IPT PDF datasheet #5
- PIC18F96J60-IPT PDF datasheet #6
- PIC18F97J60-IPF PDF datasheet #7
- Current page: 271 of 472
- Download datasheet (8Mb)
19.4.3.2
Masking an address bit causes that bit to become a
“don’t care”. When one address bit is masked, two
addresses will be Acknowledged and cause an
interrupt. It is possible to mask more than one address
bit at a time, which makes it possible to Acknowledge
up to 31 addresses in 7-bit mode, and up to
63 addresses in 10-bit mode (see Example 19-2).
The I
masking is used or not. However, when address
masking is used, the I
multiple addresses and cause interrupts. When this
occurs, it is necessary to determine which address
caused the interrupt by checking SSPxBUF.
In 7-Bit Addressing mode, address mask bits,
ADMSK<5:1> (SSPxCON2<5:1>), mask the corre-
sponding address bits in the SSPxADD register. For any
ADMSK bits that are set (ADMSK<n> = 1), the corre-
sponding address bit is ignored (SSPxADD<n> = x). For
the module to issue an address Acknowledge, it is
sufficient to match only on addresses that do not have an
active address mask.
EXAMPLE 19-2:
© 2006 Microchip Technology Inc.
7-Bit Addressing:
10-Bit Addressing:
2
C Slave behaves the same way whether address
SSPxADD<7:1> = A0h (1010000) (SSPxADD<0> is assumed to be ‘0’)
ADMSK<5:1>
Addresses Acknowledged: A0h, A2h, A4h, A6h, A8h, AAh, ACh, AEh
SSPxADD<7:0> = A0h (10100000) (the two MSb of the address are ignored in this example since they are
not affected by masking)
ADMSK<5:1>
Addresses Acknowledged: A0h, A1h, A2h, A3h, A4h, A5h, A6h, A7h, A8h, A9h, AAh, ABh, ACh, ADh, AEh, AFh
Address Masking
ADDRESS MASKING EXAMPLES
= 00111
= 00111
2
C slave can Acknowledge
Preliminary
PIC18F97J60 FAMILY
In 10-Bit Addressing mode, bits ADMSK<5:2> mask
the corresponding address bits in the SSPxADD regis-
ter. In addition, ADMSK1 simultaneously masks the two
LSbs of the address (SSPxADD<1:0>). For any
ADMSK bits that are active (ADMSK<n> = 1), the cor-
responding address bit is ignored (SSPxADD<n> = x).
Also note, that although in 10-Bit Addressing mode, the
upper address bits reuse part of the SSPxADD register
bits. The address mask bits do not interact with those
bits; they only affect the lower address bits.
Note 1: ADMSK1 masks the two Least Significant
2: The two Most Significant bits of the
bits of the address.
address are not affected by address
masking.
DS39762B-page 269
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