PIC18F97J60-I/PF Microchip Technology, PIC18F97J60-I/PF Datasheet - Page 315

• Manufacturer Part Number: PIC18F97J60-I/PF
• Description: IC PIC MCU FLASH 65KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F97J60-I/PF

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Operating Supply Voltage: 2.35 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Package: 100TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 41.667 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100DM163024 - BOARD DEMO PICDEM.NET 2
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

FIGURE 20-6:
FIGURE 20-7:
TABLE 20-6:
© 2006 Microchip Technology Inc.
INTCON
PIR1
PIE1
IPR1
PIR3
PIE3
IPR3
RCSTAx
RCREGx
TXSTAx
BAUDCONx ABDOVF
SPBRGHx
SPBRGx
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Note 1:
Name
Note:
RXx (pin)
Rcv Shift Reg
Rcv Buffer Reg
Read Rcv
Buffer Reg
RCREGx
RCxIF
(Interrupt Flag)
OERR bit
CREN
This timing diagram shows three words appearing on the RXx input. The RCREGx (Receive Buffer) is read after the third word
causing the OERR (Overrun Error) bit to be set.
These bits are only available in 80-pin and 100-pin devices; otherwise, they are unimplemented and read as ‘0’.
RXx
BRG16
EUSARTx Receive Register
EUSARTx Baud Rate Generator Register High Byte
EUSARTx Baud Rate Generator Register Low Byte
GIE/GIEH PEIE/GIEL TMR0IE
SSP2IF
SSP2IE
SSP2IP
PSPIF
PSPIE
PSPIP
SPEN
CSRC
Bit 7
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTIO
EUSARTx RECEIVE BLOCK DIAGRAM
ASYNCHRONOUS RECEPTION, RXDTP = 0 (RXx NOT INVERTED)
Start
SPBRGHx
bit
Baud Rate Generator
x64 Baud Rate CLK
RXDTP
BCL2IF
BCL2IE
BCL2IP
RCIDL
and Control
bit 0
ADIE
ADIP
Bit 6
ADIF
Pin Buffer
RX9
TX9
SPBRGx
SPEN
bit 1
RC2IF
RC2IE
RC2IP
RXDTP
RC1IE
RC1IP
RC1IF
SREN
TXEN
Bit 5
(1)
(1)
(1)
bit 7/8
Recovery
TXCKP
INT0IE
Interrupt
CREN
TX1IF
TX1IE
TX1IP
TX2IF
TX2IE
TX2IP
SYNC
Data
Bit 4
Preliminary
or
or
Stop
64
16
4
bit
CREN
Word 1
RCREGx
Start
bit
TMR4IF
TMR4IE
TMR4IP
SSP1IF
SSP1IE
SSP1IP
ADDEN
SENDB
BRG16
RBIE
Bit 3
PIC18F97J60 FAMILY
bit 0
RX9
MSb
Stop
TMR0IF
CCP1IE
CCP1IP
CCP5IE
CCP5IP
CCP1IF
CCP5IF
RCxIF
RCxIE
BRGH
FERR
Bit 2
RX9D
—
bit 7/8
(8)
Word 2
RCREGx
OERR
7
RSR Register
TMR2IF
TMR2IE TMR1IE
TMR2IP TMR1IP
CCP4IE
CCP4IP
CCP4IF
Stop
INT0IF
OERR
TRMT
RCREGx Register
bit
WUE
Bit 1
8
Start
bit
Data Bus
TMR1IF
CCP3IE
CCP3IP
CCP3IF
ABDEN
1
RX9D
TX9D
N
RBIF
Bit 0
FERR
0
bit 7/8
DS39762B-page 313
Start
LSb
FIFO
Reset Values
on Page:
Stop
bit
59
61
61
61
61
61
61
61
61
61
62
62
62