PIC18F97J60-I/PF Microchip Technology, PIC18F97J60-I/PF Datasheet - Page 459

• Manufacturer Part Number: PIC18F97J60-I/PF
• Description: IC PIC MCU FLASH 65KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F97J60-I/PF

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Operating Supply Voltage: 2.35 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Package: 100TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 41.667 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100DM163024 - BOARD DEMO PICDEM.NET 2
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Data Memory ..................................................................... 76
Data Memory
DAW ................................................................................. 376
DC and AC Characteristics
DC Characteristics ........................................................... 421
DCFSNZ .......................................................................... 377
DECF ............................................................................... 376
DECFSZ ........................................................................... 377
Default System Clock ......................................................... 44
Development Support ...................................................... 407
Device Differences ........................................................... 453
Device Overview .................................................................. 7
Direct Addressing ............................................................... 89
E
ECCP2
Effect on Standard PIC Instructions ................................. 404
Electrical Characteristics .................................................. 411
Enhanced Capture/Compare/PWM (ECCP) .................... 189
Enhanced Universal Synchronous Asynchronous
ENVREG pin .................................................................... 352
Equations
© 2006 Microchip Technology Inc.
Access Bank .............................................................. 78
Bank Select Register (BSR) ....................................... 76
Ethernet SFRs ........................................................... 80
Extended Instruction Set ............................................ 90
General Purpose Register File ................................... 78
Memory Maps
Special Function Registers ........................................ 79
Memory Maps
Graphs and Tables .................................................. 447
Power-Down and Supply Current ............................ 414
Supply Voltage ......................................................... 413
Details on Individual Family Members ......................... 8
Features (100-Pin Devices) ....................................... 10
Features (64-Pin Devices) ........................................... 9
Features (80-Pin Devices) ........................................... 9
Pin Assignment ........................................................ 182
Requirements for Ethernet Transceiver
Associated Registers ............................................... 204
Capture and Compare Modes .................................. 192
Capture Mode. See Capture (ECCP Module).
ECCP1/ECCP3 Outputs and
ECCP2 Outputs and
Enhanced PWM Mode ............................................. 193
Outputs and Configuration ....................................... 190
Pin Configurations for ECCP1 ................................. 191
Pin Configurations for ECCP2 ................................. 191
Pin Configurations for ECCP3 ................................. 192
PWM Mode. See PWM (ECCP Module).
Standard PWM Mode ............................................... 192
Timer Resources ...................................................... 190
Use of CCP4/CCP5 with ECCP1/ECCP3 ................ 190
Receiver Transmitter (EUSART). See EUSART.
A/D Acquisition Time ................................................ 328
A/D Minimum Charging Time ................................... 328
Calculating the A/D Minimum Required
Random Access Address Calculation ...................... 238
Receive Buffer Free Space Calculation ................... 239
PIC18F97J60 Family ......................................... 77
Special Function Registers ................................ 79
Ethernet Special Function Registers ................. 80
External Magnetics .......................................... 445
Program Memory Mode ................................... 190
Program Memory Modes ................................. 190
Acquisition Time .............................................. 328
Preliminary
PIC18F97J60 FAMILY
Errata ................................................................................... 6
Ethernet Module .............................................................. 205
Ethernet Operation, Microcontroller Clock ......................... 41
Associated Registers, Direct Memory
Associated Registers, Flow Control ......................... 243
Associated Registers, Reception ............................. 240
Associated Registers, Transmission ....................... 240
Buffer and Buffer Pointers ....................................... 209
Buffer and Register Spaces ..................................... 208
Buffer Organization .................................................. 209
CRC ......................................................................... 233
Direct Memory Access Controller ............................ 250
Disabling .................................................................. 231
Duplex Mode Configuration and
Ethernet and Microcontroller Memory
Ethernet Control Registers ...................................... 212
Flow Control ............................................................ 242
Initializing ................................................................. 230
Interrupts ................................................................. 224
Interrupts and Wake-on-LAN ................................... 229
LED Configuration ................................................... 206
MAC and MII Registers ........................................... 214
Magnetics, Termination and Other
Oscillator Requirements .......................................... 206
Packet Format ......................................................... 232
Per-Packet Control Bytes ........................................ 234
PHSTAT Registers .................................................. 217
PHY Register Summary .......................................... 219
PHY Registers ......................................................... 217
PHY Start-up Timer ................................................. 206
Receive Filters ......................................................... 244
Resets ..................................................................... 252
Signal and Power Interfaces .................................... 206
Special Function Registers (SFRs) ......................... 212
Transmitting and Receiving Data ............................ 232
Access Controller ............................................ 251
Buffer Arbiter ................................................... 211
DMA Access .................................................... 211
Receive Buffer ................................................. 210
Transmit Buffer ................................................ 211
Checksum Calculations ................................... 251
Copying Memory ............................................. 250
Negotiation ...................................................... 241
Relationship ..................................................... 208
External Components ...................................... 207
Broadcast ........................................................ 244
Hash Table ...................................................... 244
Magic Packet ................................................... 244
Multicast .......................................................... 244
Pattern Match .................................................. 244
Unicast ............................................................ 244
Microcontroller Reset ....................................... 252
Receive Only ................................................... 252
Transmit Only .................................................. 252
Packet Field Definitions ........................... 232–233
Reading Received Packets ............................. 238
Receive Buffer Space ...................................... 239
Receive Packet Layout .................................... 237
Receive Status Vectors ................................... 238
Receiving Packets ........................................... 237
Transmit Packet Layout ................................... 235
Transmit Status Vectors .................................. 236
Transmitting Packets ....................................... 234
DS39762B-page 457