PIC18F97J60-I/PF Microchip Technology, PIC18F97J60-I/PF Datasheet - Page 234

• Manufacturer Part Number: PIC18F97J60-I/PF
• Description: IC PIC MCU FLASH 65KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F97J60-I/PF

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Operating Supply Voltage: 2.35 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Package: 100TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 41.667 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100DM163024 - BOARD DEMO PICDEM.NET 2
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F97J60 FAMILY
18.5
The Ethernet protocol (IEEE Standard 802.3) provides
an extremely detailed description of the 10 Mbps,
frame-based serial communications system. Before
discussing the actual use of the Ethernet module, a
brief review of the structure of a typical Ethernet data
frame may be appropriate. It is assumed that users
already have some familiarity with IEEE 802.3. Those
requiring more information should refer to the official
standard, or other Ethernet reference texts, for a more
comprehensive explanation.
18.5.1
Normal IEEE 802.3 compliant Ethernet frames are
between 64 and 1518 bytes long. They are made up of
five or six different fields: a destination MAC address, a
source MAC address, a type/length field, data payload,
an optional padding field and a Cyclic Redundancy
Check (CRC). Additionally, when transmitted on the
FIGURE 18-7:
DS39762B-page 232
Note 1: The FCS is transmitted starting with bit 31 and ending with bit 0.
Used in the
Calculation
of the FCS
Transmitting and Receiving Data
PACKET FORMAT
ETHERNET PACKET FORMAT
46-1500
Number
of Bytes
7
1
6
6
2
4
Type/Length
Preamble
Padding
FCS
Field
Data
SFD
DA
SA
(1)
Preliminary
Ethernet medium, a 7-byte preamble field and
Start-of-Frame delimiter byte are appended to the
beginning of the Ethernet packet. Thus, traffic seen on
the twisted-pair cabling will appear as shown in
Figure 18-7.
18.5.1.1
When transmitting and receiving data with the Ethernet
module, the preamble and Start-of-Frame delimiter
bytes are automatically generated, or stripped from the
packets, when they are transmitted or received. It can
also automatically generate CRC fields and padding as
needed on transmission, and verify CRC data on
reception. The user application does not need to create
or process these fields, or manually verify CRC data.
However, the padding and CRC fields are written into
the receive buffer when packets arrive, so they may be
evaluated by the user application as needed.
Filtered out by the Module
Start-of-Frame Delimiter
(filtered out by the module)
Destination Address,
such as Multicast, Broadcast or Unicast
Source Address
Type of Packet or the Length of the Packet
Packet Payload
(with optional padding)
Frame Check Sequence – CRC
Preamble/Start-of-Frame Delimiter
Comments
© 2006 Microchip Technology Inc.