PIC18F97J60-I/PF Microchip Technology, PIC18F97J60-I/PF Datasheet - Page 242

• Manufacturer Part Number: PIC18F97J60-I/PF
• Description: IC PIC MCU FLASH 65KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F97J60-I/PF

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Operating Supply Voltage: 2.35 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Package: 100TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 41.667 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100DM163024 - BOARD DEMO PICDEM.NET 2
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F97J60 FAMILY
TABLE 18-6:
TABLE 18-7:
DS39762B-page 240
EIE
EIR
ESTAT
ECON1
ETXSTL
ETXSTH
ETXNDL
ETXNDH
MACON1
MACON3
MACON4
MABBIPG
MAIPGL
MAIPGH
MAMXFLL
MAMXFLH
Legend:
EIE
EIR
ESTAT
ECON2
ECON1
ERXSTL
ERXSTH
ERXNDL
ERXNDH
ERXRDPTL Receive Buffer Read Pointer Low Byte (ERXRDPT<7:0>)
ERXRDPTH
ERXFCON
EPKTCNT
MACON1
MACON3
MAMXFLL
MAMXFLH
Legend:
Register
Register
Name
Name
— = unimplemented, r = reserved bit. Shaded cells are not used.
— = unimplemented, r = reserved bit. Shaded cells are not used.
Transmit Start Register Low Byte (ETXST<7:0>)
Transmit End Register Low Byte (ETXND<7:0>)
Maximum Frame Length Register Low Byte (MAMXFL<7:0>)
Maximum Frame Length Register High Byte (MAMXFL<15:8>)
PADCFG2 PADCFG1 PADCFG0 TXCRCEN
Receive Start Register Low Byte (ERXST<7:0>)
Receive End Register Low Byte (ERXND<7:0>)
Ethernet Packet Count Register
Maximum Frame Length Register Low Byte (MAMXFL<7:0>)
Maximum Frame Length Register High Byte (MAMXFL<15:8>)
PADCFG2 PADCFG1 PADCFG0 TXCRCEN PHDREN
AUTOINC
TXRST
TXRST
UCEN
Bit 7
Bit 7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SUMMARY OF REGISTERS ASSOCIATED WITH PACKET TRANSMISSION
SUMMARY OF REGISTERS ASSOCIATED WITH PACKET RECEPTION
MAC Non Back-to-Back Inter-Packet Gap Register Low Byte (MAIPGL<6:0>)
MAC Non Back-to-Back Inter-Packet Gap Register High Byte (MAIPGH<6:0>)
BBIPG6
BUFER
RXRST
DEFER
PKTDEC
PKTIE
PKTIF
ANDOR
BUFER
RXRST
Bit 6
PKTIE
PKTIF
Bit 6
—
—
—
—
—
—
—
BBIPG5
DMAST
DMAIE
DMAIF
Bit 5
DMAST
CRCEN
ETHEN
DMAIE
DMAIF
—
—
—
—
Bit 5
r
—
—
—
—
—
Transmit Start Register High Byte (ETXST<12:8>)
Transmit End Register High Byte (ETXND<12:8>)
CSUMEN
BBIPG4
Receive Start Register High Byte (ERXST<12:8>)
Receive End Register High Byte (ERXND<12:8>)
Receive Buffer Read Pointer High Byte (ERXRDPT<12:8>)
LINKIE
LINKIF
CSUMEN
Bit 4
LINKIE
LINKIF
PMEN
Preliminary
Bit 4
r
r
r
—
r
r
PHDREN
TXPAUS
BBIPG3
TXRTS
TXPAUS
Bit 3
TXIE
TXIF
TXRTS
MPEN
—
—
Bit 3
TXIE
TXIF
—
—
HFRMEN
RXBUSY
RXPAUS
BBIPG2
HFRMEN FRMLNEN
RXBUSY
RXPAUS
RXEN
Bit 2
RXEN
HTEN
Bit 2
—
—
—
—
—
—
FRMLNEN
PASSALL
TXABRT
PASSALL
TXERIE
BBIPG1
TXERIF
TXABRT
TXERIE
TXERIF
MCEN
Bit 1
Bit 1
—
© 2006 Microchip Technology Inc.
—
—
r
MARXEN
PHYRDY
MARXEN
PHYRDY
FULDPX
FULDPX
RXERIE
RXERIF
BBIPG0
RXERIE
RXERIF
BCEN
Bit 0
Bit 0
—
—
—
r
Values on
Values on
Reset
Page:
Reset
Page:
63
63
63
60
64
64
64
64
65
65
65
65
65
65
64
64
63
63
63
63
60
64
64
64
64
63
63
64
64
65
65
64
64