PIC18F97J60-I/PF Microchip Technology, PIC18F97J60-I/PF Datasheet - Page 311

• Manufacturer Part Number: PIC18F97J60-I/PF
• Description: IC PIC MCU FLASH 65KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F97J60-I/PF

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Operating Supply Voltage: 2.35 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Package: 100TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 41.667 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100DM163024 - BOARD DEMO PICDEM.NET 2
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

20.2
The Asynchronous mode of operation is selected by
clearing the SYNC bit (TXSTAx<4>). In this mode, the
EUSARTx uses standard Non-Return-to-Zero (NRZ)
format (one Start bit, eight or nine data bits and one
Stop bit). The most common data format is 8 bits. An
on-chip, dedicated 8-bit/16-bit Baud Rate Generator
can be used to derive standard baud rate frequencies
from the oscillator.
The EUSARTx transmits and receives the LSb first.
The EUSARTx module’s transmitter and receiver are
functionally independent but use the same data format
and baud rate. The Baud Rate Generator produces a
clock, either x16 or x64 of the bit shift rate, depending
on the BRGH and BRG16 bits (TXSTAx<2> and
BAUDCONx<3>). Parity is not supported by the
hardware but can be implemented in software and
stored as the 9th data bit.
The
(BAUDCONx<5>) bits allow the TXx and RXx signals
to be inverted (polarity reversed). Devices that buffer
signals between TTL and RS-232 levels also invert the
signal. Setting the TXCKP and RXDTP bits allows for
the use of circuits that provide buffering without
inverting the signal.
When operating in Asynchronous mode, the EUSARTx
module consists of the following important elements:
• Baud Rate Generator
• Sampling Circuit
• Asynchronous Transmitter
• Asynchronous Receiver
• Auto-Wake-up on Sync Break Character
• 12-Bit Break Character Transmit
• Auto-Baud Rate Detection
20.2.1
The EUSARTx transmitter block diagram is shown in
Figure 20-3. The heart of the transmitter is the Transmit
(Serial) Shift Register (TSR). The Shift register obtains
its data from the Read/Write Transmit Buffer register,
TXREGx. The TXREGx register is loaded with data in
software. The TSR register is not loaded until the Stop
bit has been transmitted from the previous load. As
soon as the Stop bit is transmitted, the TSR is loaded
with new data from the TXREGx register (if available).
© 2006 Microchip Technology Inc.
TXCKP
EUSARTx Asynchronous Mode
EUSARTx ASYNCHRONOUS
TRANSMITTER
(BAUDCONx<4>)
and
RXDTP
Preliminary
PIC18F97J60 FAMILY
Once the TXREGx register transfers the data to the
TSR register (occurs in one T
is empty and the TXxIF flag bit is set. This interrupt can
be enabled or disabled by setting or clearing the inter-
rupt enable bit, TXxIE. TXxIF will be set regardless of
the state of TXxIE; it cannot be cleared in software.
TXxIF is also not cleared immediately upon loading
TXREGx, but becomes valid in the second instruction
cycle following the load instruction. Polling TXxIF
immediately following a load of TXREGx will return
invalid results.
While TXxIF indicates the status of the TXREGx regis-
ter, another bit, TRMT (TXSTAx<1>), shows the status
of the TSR register. TRMT is a read-only bit which is set
when the TSR register is empty. No interrupt logic is
tied to this bit so the user has to poll this bit in order to
determine if the TSR register is empty.
To set up an Asynchronous Transmission:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Note 1: The TSR register is not mapped in data
Initialize the SPBRGHx:SPBRGx registers for
the appropriate baud rate. Set or clear the
BRGH and BRG16 bits, as required, to achieve
the desired baud rate.
Enable the asynchronous serial port by clearing
the SYNC bit and setting bit, SPEN.
If the signal from the TXx pin is to be inverted,
set the TXCKP bit.
If interrupts are desired, set enable bit, TXxIE.
If 9-bit transmission is desired, set transmit bit,
TX9. Can be used as address/data bit.
Enable the transmission by setting the TXEN bit
which will also set bit, TXxIF.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit, TX9D.
Load data to the TXREGx register (starts
transmission).
If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
2: Flag bit, TXxIF, is set when enable bit
memory, so it is not available to the user.
TXEN is set.
CY
), the TXREGx register
DS39762B-page 309