PIC18F97J60-I/PF Microchip Technology, PIC18F97J60-I/PF Datasheet - Page 149

• Manufacturer Part Number: PIC18F97J60-I/PF
• Description: IC PIC MCU FLASH 65KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F97J60-I/PF

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Operating Supply Voltage: 2.35 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Package: 100TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 41.667 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100DM163024 - BOARD DEMO PICDEM.NET 2
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

10.6
PORTE is implemented as a bidirectional port in two
different ways:
• 64-pin devices: 6 bits wide (RE<5:0>)
• 80-pin and 100-pin devices: 8 bits wide (RE<7:0>)
The corresponding Data Direction register is TRISE.
Setting a TRISE bit (= 1) will make the corresponding
PORTE pin an input (i.e., put the corresponding output
driver in a high-impedance mode). Clearing a TRISE bit
(= 0) will make the corresponding PORTE pin an output
(i.e., put the contents of the output latch on the selected
pin). All pins on PORTE are digital only and tolerate
voltages up to 5.5V.
The Output Latch register (LATE) is also memory
mapped. Read-modify-write operations on the LATE
register read and write the latched output value for
PORTE.
All pins on PORTE are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
On 100-pin devices, PORTE is multiplexed with the
system bus as part of the external memory interface.
I/O port and other functions are only available when the
interface is disabled by setting the EBDIS bit
(MEMCON<7>). When the interface is enabled,
PORTE is the high-order byte of the multiplexed
address/data bus (AD15:AD8). The TRISE bits are also
overridden.
Each of the PORTE pins has a weak internal pull-up. A
single control bit can turn on all of the pull-ups. This is
performed by setting bit REPU (LATA<6>). The weak
pull-up is automatically turned off when the port pin is
configured as an output. The pull-ups are disabled on
all device Resets.
© 2006 Microchip Technology Inc.
Note:
PORTE, TRISE and
LATE Registers
These pins are configured as digital inputs
on any device Reset.
Preliminary
PIC18F97J60 FAMILY
PORTE is also multiplexed with Enhanced PWM
outputs B and C for ECCP1 and ECCP3 and outputs B,
C and D for ECCP2. For 80-pin and 100-pin devices,
their default assignments are on PORTE<6:0>. For
64-pin devices, their default assignments are on
PORTE<5:0> and PORTD<0>. On 80-pin and 100-pin
devices, the multiplexing for the outputs of ECCP1 and
ECCP3 is controlled by the ECCPMX Configuration bit.
Clearing this bit reassigns the P1B/P1C and P3B/P3C
outputs to PORTH.
For 80-pin and 100-pin devices operating in Micro-
controller mode, pin RE7 can be configured as the
alternate peripheral pin for the ECCP2 module and
Enhanced PWM output 2A. This is done by clearing the
CCP2MX Configuration bit.
When the Parallel Slave Port is active on PORTD,
three of the PORTE pins (RE0, RE1 and RE2) are con-
figured as digital control inputs for the port. The control
functions are summarized in Table 10-11. The reconfig-
uration occurs automatically when the PSPMODE
control bit (PSPCON<4>) is set. Users must still make
certain the corresponding TRISE bits are set to
configure these pins as digital inputs.
EXAMPLE 10-5:
CLRF
CLRF
MOVLW
MOVWF
PORTE
LATE
03h
TRISE
; Initialize PORTE by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RE<1:0> as inputs
; RE<7:2> as outputs
INITIALIZING PORTE
DS39762B-page 147