PIC18F97J60-I/PF Microchip Technology, PIC18F97J60-I/PF Datasheet - Page 240

• Manufacturer Part Number: PIC18F97J60-I/PF
• Description: IC PIC MCU FLASH 65KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F97J60-I/PF

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Operating Supply Voltage: 2.35 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Package: 100TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 41.667 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100DM163024 - BOARD DEMO PICDEM.NET 2
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F97J60 FAMILY
TABLE 18-5:
18.5.3.2
To process the packet, an application will normally start
reading from the beginning of the Next Packet Pointer.
The application will save the Next Packet Pointer, any
necessary bytes from the receive status vector, and
then proceed to read the actual packet contents. If the
AUTOINC bit is set, it will be able to sequentially read
the entire packet without ever modifying the ERDPT
registers. The Read Pointer would automatically wrap
at the end of the circular receive buffer to the beginning.
EQUATION 18-1:
DS39762B-page 238
If Packet Start Address + Offset > ERXND, then
else
15-0
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Zero
Receive VLAN Type Detected
Receive Unknown Opcode
Receive Pause Control Frame
Receive Control Frame
Dribble Nibble
Receive Broadcast Packet
Receive Multicast Packet
Received OK
Length Out of Range
Length Check Error
CRC Error
Reserved
Carrier Event Previously Seen
Reserved
Long Event/Drop Event
Received Byte Count
Reading Received Packets
ERDPT = Packet Start Address + Offset – (ERXND – ERXST + 1)
ERDPT = Packet Start Address + Offset
RECEIVE STATUS VECTORS
RANDOM ACCESS ADDRESS CALCULATION
Field
‘0’
Current frame was recognized as a VLAN tagged frame.
Current frame was recognized as a control frame but it contained an
unknown opcode.
Current frame was recognized as a control frame containing a valid pause
frame opcode and a valid destination address.
Current frame was recognized as a control frame for having a valid
type/length designating it as a control frame.
Indicates that after the end of this packet, an additional 1 to 7 bits were
received. The extra bits were thrown away.
Indicates packet received had a valid Broadcast address.
Indicates packet received had a valid Multicast address.
Indicates that the packet had a valid CRC and no symbol errors.
Indicates that frame type/length field was larger than 1500 bytes
(type field).
Indicates that frame length field value in the packet does not match the
actual data byte length.
Indicates that the frame CRC field value does not match the CRC
calculated by the MAC.
Indicates that at some time since the last receive, a carrier event was
detected. The carrier event is not associated with this packet. A carrier
event is activity on the receive channel that does not result in a packet
receive attempt being made.
Indicates a packet over 50,000 bit times occurred or that a packet was
dropped since the last receive.
Indicates length of the received frame. This includes the destination
address, source address, type/length, data, padding and CRC fields. This
field is stored in little-endian format.
Preliminary
In the event that the application needed to randomly
access the packet, it would be necessary to manually
calculate the proper ERDPT registers, taking care to
not exceed the end of the receive buffer, if the packet
spans the ERXND to ERXST buffer boundary. In other
words, given the packet start address and a desired
offset, the application should follow the logic shown in
Equation 18-1.
Description
© 2006 Microchip Technology Inc.