PIC18F97J60-I/PF Microchip Technology, PIC18F97J60-I/PF Datasheet - Page 445

• Manufacturer Part Number: PIC18F97J60-I/PF
• Description: IC PIC MCU FLASH 65KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F97J60-I/PF

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Operating Supply Voltage: 2.35 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Package: 100TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 41.667 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100DM163024 - BOARD DEMO PICDEM.NET 2
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

FIGURE 27-19:
TABLE 27-24: EUSARTx SYNCHRONOUS TRANSMISSION REQUIREMENTS
FIGURE 27-20:
TABLE 27-25: EUSARTx SYNCHRONOUS RECEIVE REQUIREMENTS
© 2006 Microchip Technology Inc.
120
121
122
125
126
Param
Param.
No.
No.
Note:
RXx/DTx
TXx/CKx
Note:
T
T
T
RXx/DTx
TXx/CKx
T
T
CK
CKRF
Symbol
DTRF
Symbol
CK
DT
pin
pin
H2
L2
V2
Refer to Figure 27-3 for load conditions.
DT
pin
pin
DTL
CKL
V SYNC XMIT (MASTER and SLAVE)
Refer to Figure 27-3 for load conditions.
Clock High to Data Out Valid
Clock Out Rise Time and Fall Time (Master mode)
Data Out Rise Time and Fall Time
SYNC RCV (MASTER and SLAVE)
Data Hold before CKx
Data Hold after CKx
EUSARTx SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
EUSARTx SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
120
Characteristic
121
Characteristic
125
(DTx hold time)
(DTx hold time)
Preliminary
121
PIC18F97J60 FAMILY
126
Min
10
15
Min
Max
—
—
—
—
—
122
Units
Max
ns
ns
20
20
40
Units
ns
ns
ns
DS39762B-page 443
Conditions
Conditions