PIC18F97J60-I/PF Microchip Technology, PIC18F97J60-I/PF Datasheet - Page 239

• Manufacturer Part Number: PIC18F97J60-I/PF
• Description: IC PIC MCU FLASH 65KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F97J60-I/PF

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Operating Supply Voltage: 2.35 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Package: 100TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 41.667 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100DM163024 - BOARD DEMO PICDEM.NET 2
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

18.5.3
Assuming that the receive buffer has been initialized,
the MAC has been properly configured and the receive
filters have been configured, the application should
perform these steps to receive Ethernet packets:
1.
2.
3.
After setting RXEN, the Duplex mode and the Receive
Buffer Start and End Pointers should not be modified.
Additionally, to prevent unexpected packets from arriv-
ing, it is recommended that RXEN be cleared before
altering the receive filter configuration (ERXFCON) and
MAC address.
After reception is enabled, packets which are not
filtered out will be written into the circular receive buffer.
Any packet which does not meet the necessary filter
FIGURE 18-10:
© 2006 Microchip Technology Inc.
Set the PKTIE and ETHIE bits to generate an
Ethernet interrupt whenever a packet is received
(if desired).
Clear the RXERIF flag and set both RXERIE
and ETHIE to generate an interrupt whenever a
packet is dropped due to insufficient buffer
space or memory access bandwidth (if desired).
Enable reception by setting the RXEN bit
(ECON1<2>).
Packet N + 1
Packet N – 1
RECEIVING PACKETS
Packet N
SAMPLE RECEIVE PACKET LAYOUT
Address
106Ch
106Dh
101Fh
106Ah
106Bh
106Eh
1020h
1021h
1022h
1023h
1024h
1025h
1026h
1027h
1059h
rsv[23:16]
rsv[30:24]
data[m-3]
data[m-2]
data[m-1]
Memory
rsv[15:8]
rsv[7:0]
data[m]
data[1]
data[2]
6Eh
10h
Preliminary
status[23:16]
status[31:24]
status[15:8]
status[7:0]
High Byte
crc[31:24]
crc[23:16]
Low Byte
crc[15:8]
crc[7:0]
PIC18F97J60 FAMILY
criteria will be discarded and the application will not
have any means of identifying that a packet was thrown
away. When a packet is accepted and completely
written into the buffer:
• the EPKTCNT register is incremented,
• the PKTIF bit is set,
• an interrupt is generated (if enabled), and
• the Hardware Write Pointers, ERXWRPT, are
18.5.3.1
Figure 18-10 shows the layout of a received packet.
The packets are preceded by a 6-byte header which
contains a Next Packet Pointer in addition to a receive
status vector which contains receive statistics,
including the packet’s size. The receive status vectors
are shown in Table 18-5.
If the last byte in the packet ends on an odd value
address, the hardware will automatically add a padding
byte when advancing the Hardware Write Pointer. As
such, all packets will start on an even boundary.
automatically advanced.
Description
End of the Previous Packet
Next Packet Pointer
Receive Status Vector
Packet Data: Destination Address,
Source Address, Type/Length, Data,
Padding, CRC
Byte Skipped to Ensure
Even Buffer Address
Start of the Next Packet
Receive Packet Layout
DS39762B-page 237