PIC18F97J60-I/PF Microchip Technology, PIC18F97J60-I/PF Datasheet - Page 160

• Manufacturer Part Number: PIC18F97J60-I/PF
• Description: IC PIC MCU FLASH 65KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F97J60-I/PF

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Operating Supply Voltage: 2.35 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Package: 100TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 41.667 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100DM163024 - BOARD DEMO PICDEM.NET 2
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F97J60 FAMILY
TABLE 10-19: PORTJ FUNCTIONS
TABLE 10-20: SUMMARY OF REGISTERS ASSOCIATED WITH PORTJ
DS39762B-page 158
PORTJ
LATJ
TRISJ
PORTA
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTJ.
Note 1:
RJ0/ALE
RJ1/OE
RJ2/WRL
RJ3/WRH
RJ4/BA0
RJ5/CE
RJ6/LB
RJ7/UB
Legend:
Note 1:
Name
Pin Name
2:
(1)
(1)
(1)
(1)
(1)
(1)
Implemented on 100-pin devices only.
O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Implemented on 100-pin devices only.
EMB functions are implemented on 100-pin devices only.
TRISJ7
LATJ7
RJ7
RJPU
Bit 7
Function
WRH
WRL
(1)
ALE
BA0
RJ0
RJ1
RJ2
RJ3
RJ6
RJ7
OE
CE
UB
LB
RJ4
RJ5
(1)
(1)
(1)
(1)
(2)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(2)
(1)
(1)
TRISJ6
LATJ6
RJ6
Bit 6
—
Setting
(1)
TRIS
(1)
(1)
0
1
x
0
1
x
0
1
x
0
1
x
0
1
x
0
1
x
0
1
x
0
1
x
TRISJ5
LATJ5
Bit 5
RA5
RJ5
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
Type
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
I/O
ST
ST
ST
ST
ST
ST
ST
ST
TRISJ4
LATJ4
Bit 4
RA4
RJ4
Preliminary
LATJ<0> data output.
PORTJ<0> data input; weak pull-up when RJPU bit is set.
External memory interface address latch enable control output; takes
priority over digital I/O.
LATJ<1> data output.
PORTJ<1> data input; weak pull-up when RJPU bit is set.
External memory interface output enable control output; takes priority
over digital I/O.
LATJ<2> data output.
PORTJ<2> data input; weak pull-up when RJPU bit is set.
External memory bus write low byte control; takes priority over
digital I/O.
LATJ<3> data output.
PORTJ<3> data input; weak pull-up when RJPU bit is set.
External memory interface write high byte control output; takes priority
over digital I/O.
LATJ<4> data output.
PORTJ<4> data input; weak pull-up when RJPU bit is set.
External memory interface byte address 0 control output; takes priority
over digital I/O.
LATJ<5> data output.
PORTJ<5> data input; weak pull-up when RJPU bit is set.
External memory interface chip enable control output; takes priority
over digital I/O.
LATJ<6> data output.
PORTJ<6> data input; weak pull-up when RJPU bit is set.
External memory interface lower byte enable control output; takes
priority over digital I/O.
LATJ<7> data output.
PORTJ<7> data input; weak pull-up when RJPU bit is set.
External memory interface upper byte enable control output; takes
priority over digital I/O.
TRISJ3
LATJ3
RJ3
Bit 3
RA3
(1)
(1)
(1)
TRISJ2
LATJ2
RJ2
Bit 2
RA2
(1)
(1)
(1)
Description
TRISJ1
LATJ1
RJ1
Bit 1
RA1
© 2006 Microchip Technology Inc.
(1)
(1)
(1)
TRISJ0
LATJ0
RJ0
Bit 0
RA0
(1)
(1)
(1)
on Page:
Values
Reset
62
61
61
62