PIC18F97J60-I/PF Microchip Technology, PIC18F97J60-I/PF Datasheet - Page 261
![IC PIC MCU FLASH 65KX16 100TQFP](/photos/12/13/121330/c04-100-tqfp_sml.jpg)
PIC18F97J60-I/PF
Manufacturer Part Number
PIC18F97J60-I/PF
Description
IC PIC MCU FLASH 65KX16 100TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F66J65-IPT.pdf
(8 pages)
3.PIC18F66J65-IPT.pdf
(480 pages)
4.PIC18F66J65-IPT.pdf
(4 pages)
5.PIC18F66J65-IPT.pdf
(10 pages)
6.PIC18F96J60-IPT.pdf
(24 pages)
7.PIC18F97J60-IPF.pdf
(472 pages)
Specifications of PIC18F97J60-I/PF
Program Memory Type
FLASH
Program Memory Size
128KB (64K x 16)
Package / Case
100-TQFP, 100-VQFP
Core Processor
PIC
Core Size
8-Bit
Speed
41.667MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
70
Ram Size
3808 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3808 B
Interface Type
Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
Maximum Clock Frequency
41.667 MHz
Number Of Programmable I/os
70
Number Of Timers
5
Operating Supply Voltage
2.35 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
Package
100TQFP
Device Core
PIC
Family Name
PIC18
Maximum Speed
41.667 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162064 - HEADER INTFC MPLABICD2 64/80/100DM163024 - BOARD DEMO PICDEM.NET 2
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F97J60-I/PF
Manufacturer:
MICRRCHIP
Quantity:
1 800
Company:
Part Number:
PIC18F97J60-I/PF
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F97J60-I/PF
Manufacturer:
MICROCHI
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PIC18F66J65-IPT PDF datasheet #2
- PIC18F66J65-IPT PDF datasheet #3
- PIC18F66J65-IPT PDF datasheet #4
- PIC18F66J65-IPT PDF datasheet #5
- PIC18F96J60-IPT PDF datasheet #6
- PIC18F97J60-IPF PDF datasheet #7
- Current page: 261 of 472
- Download datasheet (8Mb)
19.3.6
In Slave mode, the data is transmitted and received as
the external clock pulses appear on SCKx. When the
last bit is latched, the SSPxIF interrupt flag bit is set.
Before enabling the module in SPI Slave mode, the
clock line must match the proper Idle state. The clock
line can be observed by reading the SCKx pin. The Idle
state is determined by the CKP bit (SSPxCON1<4>).
While in Slave mode, the external clock is supplied by
the external clock source on the SCKx pin. This
external clock must meet the minimum high and low
times as specified in the electrical specifications.
While in Sleep mode, the slave can transmit/receive
data. When a byte is received, the device will wake-up
from Sleep.
19.3.7
The SSx pin allows a Synchronous Slave mode. The
SPI must be in Slave mode with SSx pin control
enabled (SSPxCON1<3:0> = 04h). When the SSx pin
is low, transmission and reception are enabled and the
FIGURE 19-4:
© 2006 Microchip Technology Inc.
SSx
SCKx
(CKP = 0
CKE = 0)
SCKx
(CKP = 1
CKE = 0)
Write to
SSPxBUF
SDOx
SDIx
(SMP = 0)
Input
Sample
(SMP = 0)
SSPxIF
Interrupt
Flag
SSPxSR to
SSPxBUF
SLAVE MODE
SLAVE SELECT
SYNCHRONIZATION
SLAVE SYNCHRONIZATION WAVEFORM
bit 7
bit 7
bit 6
Preliminary
PIC18F97J60 FAMILY
SDOx pin is driven. When the SSx pin goes high, the
SDOx pin is no longer driven, even if in the middle of a
transmitted byte, and becomes a floating output.
External pull-up/pull-down resistors may be desirable
depending on the application.
When the SPI module resets, the bit counter is forced
to ‘0’. This can be done by either forcing the SSx pin to
a high level or clearing the SSPEN bit.
To emulate two-wire communication, the SDOx pin can
be connected to the SDIx pin. When the SPI needs to
operate as a receiver, the SDOx pin can be configured
as an input. This disables transmissions from the
SDOx. The SDIx can always be left as an input (SDIx
function) since it cannot create a bus conflict.
Note 1: When the SPI is in Slave mode with SSx pin
2: If the SPI is used in Slave mode with CKE
control enabled (SSPxCON1<3:0> = 0100),
the SPI module will reset if the SSx pin is set
to V
set, then the SSx pin control must be
enabled.
bit 7
bit 7
DD
.
Next Q4 Cycle
after Q2
DS39762B-page 259
bit 0
bit 0
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