PIC18F97J60-I/PF Microchip Technology, PIC18F97J60-I/PF Datasheet - Page 185

• Manufacturer Part Number: PIC18F97J60-I/PF
• Description: IC PIC MCU FLASH 65KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F97J60-I/PF

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Operating Supply Voltage: 2.35 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Package: 100TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 41.667 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100DM163024 - BOARD DEMO PICDEM.NET 2
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

16.2
In Capture mode, the CCPRxH:CCPRxL register pair
captures the 16-bit value of the TMR1 or TMR3
registers when an event occurs on the corresponding
CCPx pin. An event is defined as one of the following:
• every falling edge
• every rising edge
• every 4th rising edge
• every 16th rising edge
The event is selected by the mode select bits,
CCPxM3:CCPxM0 (CCPxCON<3:0>). When a capture
is made, the interrupt request flag bit, CCPxIF, is set; it
must be cleared in software. If another capture occurs
before the value in register CCPRx is read, the old
captured value is overwritten by the new captured value.
16.2.1
In Capture mode, the appropriate CCPx pin should be
configured as an input by setting the corresponding
TRIS direction bit.
16.2.2
The timers that are to be used with the capture feature
(Timer1 and/or Timer3) must be running in Timer mode or
Synchronized Counter mode. In Asynchronous Counter
mode, the capture operation will not work. The timer to be
used with each CCPx module is selected in the T3CON
register (see Section 16.1.1 “CCPx/ECCPx Modules
and Timer Resources”).
FIGURE 16-2:
© 2006 Microchip Technology Inc.
Note:
Capture Mode
CCPx PIN CONFIGURATION
If RG4/CCP5/P1D is configured as an
output, a write to the port can cause a
capture condition.
TIMER1/TIMER3 MODE SELECTION
CCP4 Pin
CCP5 Pin
CAPTURE MODE OPERATION BLOCK DIAGRAM
CCP4CON<3:0>
CCP5CON<3:0>
Prescaler
Prescaler
1, 4, 16
1, 4, 16
Q1:Q4
4
Edge Detect
Edge Detect
4
4
and
and
Set CCP5IF
Preliminary
Set CCP4IF
T3CCP1
T3CCP2
T3CCP2
T3CCP1
T3CCP2
T3CCP2
PIC18F97J60 FAMILY
16.2.3
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep the
CCPxIE interrupt enable bit clear to avoid false
interrupts. The interrupt flag bit, CCPxIF, should also be
cleared following any such change in operating mode.
16.2.4
There are four prescaler settings in Capture mode.
They are specified as part of the operating mode
selected by the mode select bits (CCPxM3:CCPxM0).
Whenever the CCPx module is turned off or Capture
mode is disabled, the prescaler counter is cleared. This
means that any Reset will clear the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared; therefore, the first capture may be from
a non-zero prescaler. Example 16-1 shows the
recommended method for switching between capture
prescalers. This example also clears the prescaler
counter and will not generate the “false” interrupt.
EXAMPLE 16-1:
CLRF
MOVLW
MOVWF
CCP5CON
NEW_CAPT_PS ; Load WREG with the
CCP5CON
SOFTWARE INTERRUPT
CCPx PRESCALER
TMR3
Enable
TMR1
Enable
TMR3
Enable
TMR1
Enable
CCPR4H
CCPR5H
TMR3H
TMR1H
TMR3H
TMR1H
CHANGING BETWEEN
CAPTURE PRESCALERS
(CCP5 SHOWN)
; Turn CCP module off
; new prescaler mode
; value and CCP ON
; Load CCP5CON with
; this value
CCPR4L
CCPR5L
TMR3L
TMR1L
TMR1L
TMR3L
DS39762B-page 183