PIC18F97J60-I/PF Microchip Technology, PIC18F97J60-I/PF Datasheet - Page 283

• Manufacturer Part Number: PIC18F97J60-I/PF
• Description: IC PIC MCU FLASH 65KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F97J60-I/PF

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Operating Supply Voltage: 2.35 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Package: 100TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 41.667 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100DM163024 - BOARD DEMO PICDEM.NET 2
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

19.4.5
The addressing procedure for the I
the first byte after the Start condition usually
determines which device will be the slave addressed by
the master. The exception is the general call address,
which can address all devices. When this address is
used, all devices should, in theory, respond with an
Acknowledge.
The general call address is one of eight addresses
reserved for specific purposes by the I
consists of all ‘0’s with R/W = 0.
The general call address is recognized when the
General
(SSPxCON2<7> set). Following a Start bit detect, 8 bits
are shifted into the SSPxSR and the address is
compared against the SSPxADD. It is also compared to
the general call address and fixed in hardware.
FIGURE 19-17:
© 2006 Microchip Technology Inc.
SDAx
SCLx
SSPxIF
BF (SSPxSTAT<0>)
SSPOV (SSPxCON1<6>)
GCEN (SSPxCON2<7>)
Call
GENERAL CALL ADDRESS
SUPPORT
Enable
S
SLAVE MODE GENERAL CALL ADDRESS SEQUENCE
(7 OR 10-BIT ADDRESSING MODE)
1
bit,
2
General Call Address
GCEN,
2
3
C bus is such that
2
4
C protocol. It
is
5
enabled
6
Preliminary
7
R/W = 0
8
PIC18F97J60 FAMILY
ACK
If the general call address matches, the SSPxSR is
transferred to the SSPxBUF, the BF flag bit is set
(eighth bit) and on the falling edge of the ninth bit (ACK
bit), the SSPxIF interrupt flag bit is set.
When the interrupt is serviced, the source for the
interrupt can be checked by reading the contents of the
SSPxBUF. The value can be used to determine if the
address was device specific or a general call address.
In 10-Bit Addressing mode, the SSPxADD is required
to be updated for the second half of the address to
match and the UA bit is set (SSPxSTAT<1>). If the gen-
eral call address is sampled when the GCEN bit is set,
while the slave is configured in 10-Bit Addressing
mode, then the second half of the address is not nec-
essary, the UA bit will not be set and the slave will begin
receiving data after the Acknowledge (Figure 19-17).
Address is compared to General Call Address
after ACK, set interrupt
9
D7
1
D6
2
Cleared in software
SSPxBUF is read
Receiving Data
D5
3
D4
4
D3
5
D2
6
D1
7
DS39762B-page 281
D0
8
ACK
9
‘0’
‘1’