PIC18F97J60-I/PF Microchip Technology, PIC18F97J60-I/PF Datasheet - Page 252

• Manufacturer Part Number: PIC18F97J60-I/PF
• Description: IC PIC MCU FLASH 65KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F97J60-I/PF

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Operating Supply Voltage: 2.35 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Package: 100TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 41.667 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100DM163024 - BOARD DEMO PICDEM.NET 2
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F97J60 FAMILY
18.9
The Ethernet module incorporates a dual purpose DMA
controller, which can be used to copy data between loca-
tions within the 8-Kbyte memory buffer. It can also be
used to calculate a 16-bit checksum which is compatible
with various industry standard communication protocols,
including TCP, UDP, IP, ICMP, etc.
The DMA is controlled using three pointers and several
status/control bits:
• EDMASTH:EDMASTL: Source Start Address
• EDMANDH:EDMANDL: Source End Address
• EDMADSTH:EDMADSTL: Destination Start
• DMAST and CSUMEN (ECON1<5,4>): DMA
• DMAIE and DMAIF (EIE<5> and EIR<5>): DMA
The Source and End Pointers define what data will be
copied or checksumed. The Destination Pointer, used
only when copying data, defines where copied data will
be placed. All three pointers are with respect to the
8-Kbyte Ethernet memory and cannot be used to
access memory in the PIC
memory space.
When a DMA operation begins, the EDMAST register
pair is copied into an Internal Source Pointer. The DMA
will execute on one byte at a time and then increment the
Internal Source Pointer. However, if a byte is processed
and the Internal Source Pointer is equal to the Receive
Buffer End Pointer pair, ERXND, the Source Pointer will
not be incremented. Instead, the Internal Source Pointer
will be loaded with the Receive Buffer Start Pointer pair,
ERXST. In this way, the DMA will follow the circular FIFO
structure of the receive buffer and received packets can
be processed using one operation. The DMA operation
will end when the Internal Source Pointer matches the
EDMAND Pointers.
While any DMA operation is in progress, the DMA Point-
ers and the CSUMEN bit (ECON1<4>) should not be
modified. The DMA operation can be canceled at any
time by clearing the DMAST bit (ECON1<5>). No regis-
ters will change; however, some memory bytes may
already have been copied if a DMA copy was in progress.
Some operational requirements must always be kept in
mind when using the DMA. Failure to observe these
requirements may result in loss of Ethernet buffer data,
or even complete failure of Ethernet operation:
• If the EDMAND Pointers cannot be reached
• By design, the DMA module cannot be used to
DS39762B-page 250
Address
Start/Busy and Checksum Enable bits
Interrupt Enable and Flag bits
because of the receive buffer wrapping behavior,
the DMA operation will never end.
copy or calculate a checksum over only one byte
(EDMAST = EDMAND). An attempt to do so may
overwrite all memory in the buffer and never end.
Direct Memory Access Controller
®
microcontroller data
Preliminary
• After termination of a DMA operation (DMAST is
• To ensure reliable operation, avoid having the
18.9.1
To copy memory within the buffer:
1.
2.
3.
4.
If a transmit operation is in progress (TXRTS bit is set)
while the DMAST bit is set, the module will wait until the
transmit operation is complete before attempting to do
the DMA copy. This possible delay is required because
the DMA and transmission engine are unable to access
the buffer at the same time.
When the copy is complete, the DMA hardware will
clear the DMAST bit, set the DMAIF bit and generate
an interrupt (if enabled). The pointers and the
EDMACS registers will not be modified.
After the DMA module has been initialized and has
begun its copy, one instruction cycle (T
required for each byte copied. However, if the Ethernet
receive hardware accumulates one byte of data, the
DMA will stall that cycle, yielding to the higher priority
operation. If a maximum size, 1518-byte packet was
copied while no other memory bandwidth was being
used, the DMA module would require slightly more than
145.7 s to complete at a core frequency of 41.667
MHz. The time required to copy a minimum size packet
of 64 bytes would be approximately 6.2
41.667 MHz) plus register configuration time.
cleared by hardware or firmware), the application
must not set DMAST again within 4 instruction
cycles.
application access EDATA during a DMA copy
operation. EDATA may be safely accessed during
DMA checksum operations.
Program
EDMADST register pairs with the appropriate
start, end and destination addresses. The
EDMAST registers should point to the first byte to
copy from, the EDMAND registers should point to
the last byte to copy and the EDMADST registers
should point to the first byte in the destination
range. The destination range will always be linear,
never wrapping at any values except from 8191 to
0 (the 8-Kbyte memory boundary). Extreme care
should be taken when calculating the End Pointer
to prevent a never ending DMA operation which
would overwrite the entire 8-Kbyte buffer.
If desired, set the DMAIE (EIE<5>) and ETHIE
(PIE2<5>) bits, and clear the DMAIF (EIR<5>)
flag bit to enable an interrupt at the end of the
copy process.
Clear the CSUMEN (ECON1<4>) bit.
Start the DMA copy by setting the DMAST
(ECON1<5>) bit.
COPYING MEMORY
the
EDMAST,
© 2006 Microchip Technology Inc.
EDMAND,
CY
) will be
and
s (at