PIC18F97J60-I/PF Microchip Technology, PIC18F97J60-I/PF Datasheet - Page 81

• Manufacturer Part Number: PIC18F97J60-I/PF
• Description: IC PIC MCU FLASH 65KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F97J60-I/PF

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Operating Supply Voltage: 2.35 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Package: 100TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 41.667 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100DM163024 - BOARD DEMO PICDEM.NET 2
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.3.4
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral modules for controlling
the desired operation of the device. These registers are
implemented as static RAM.
The main group of SFRs start at the top of data memory
(FFFh) and extend downward to occupy more than the
top half of Bank 15 (F60h to FFFh). These SFRs can
be classified into two sets: those associated with the
“core” device functionality (ALU, Resets and interrupts)
and those related to the peripheral functions. The
TABLE 5-3:
© 2006 Microchip Technology Inc.
Note 1:
Address
FEDh POSTDEC0
FECh
FFEh
FFDh
FFCh
FFBh
FEFh
FEEh POSTINC0
FEBh
FEAh
FFFh
FFAh
FE9h
FE8h
FE7h
FE6h POSTINC1
FE5h POSTDEC1
FE4h
FE3h
FE2h
FE1h
FE0h
FF9h
FF8h
FF7h
FF6h
FF5h
FF4h
FF3h
FF2h
FF1h
FF0h
2:
3:
4:
PREINC0
PREINC1
This is not a physical register.
Unimplemented registers are read as ‘0’.
This register is not available on 64-pin devices.
This register is not available on 64 and 80-pin devices.
SPECIAL FUNCTION REGISTERS
PLUSW0
PLUSW1
TBLPTRU
TBLPTRH
TBLPTRL
INTCON2
INTCON3
STKPTR
PCLATU
PCLATH
INTCON
INDF0
INDF1
TABLAT
PRODH
PRODL
FSR0H
FSR1H
FSR0L
WREG
FSR1L
Name
TOSU
TOSH
TOSL
BSR
PCL
SPECIAL FUNCTION REGISTER MAP FOR PIC18F97J60 FAMILY DEVICES
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Address
FDEh POSTINC2
FDDh POSTDEC2
FDCh
FDBh
FDAh
FCEh
FCDh
FCCh
FCBh
FCAh
FDFh
FCFh
FD9h
FD8h
FD7h
FD6h
FD5h
FD4h
FD3h
FD2h
FD1h
FD0h
FC9h
FC8h
FC7h
FC6h
FC5h
FC4h
FC3h
FC2h
FC1h
FC0h
SSP1CON1
SSP1CON2
PREINC2
PLUSW2
SSP1STAT
SSP1BUF
SSP1ADD
WDTCON
OSCCON
ADRESH
ADCON0
ADCON1
ADCON2
ADRESL
INDF2
STATUS
TMR0H
T0CON
ECON1
TMR1H
T1CON
T2CON
FSR2H
TMR0L
TMR1L
FSR2L
RCON
Name
TMR2
—
PR2
(2)
(1)
(1)
(1)
(1)
(1)
Address
Preliminary
FBDh
FBCh
FBEh
FBBh
FBAh
FADh
FACh
FBFh
FAEh
FABh
FAAh
FB9h
FB8h
FB7h
FB6h
FB5h
FB4h
FB3h
FB2h
FB1h
FB0h
FAFh
FA9h
FA8h
FA7h
FA6h
FA5h
FA3h
FA2h
FA1h
FA0h
FA4h
EECON2
CCP1CON
CCP2CON
CCP3CON
ECCP1AS
CVRCON
CCPR1H
CCPR2H
CCPR3H
PSPCON
RCREG1
EECON1
CCPR1L
CCPR2L
CCPR3L
SPBRG1
TXREG1
RCSTA1
CMCON
TXSTA1
TMR3H
T3CON
TMR3L
PIC18F97J60 FAMILY
Name
IPR3
PIR3
PIE3
IPR2
PIR2
PIE2
—
—
—
Reset and Interrupt registers are described in their
respective chapters, while the ALU’s STATUS register
is described later in this section. Registers related to
the operation of the peripheral features are described
in the chapter for that peripheral.
The SFRs are typically distributed among the
peripherals whose functions they control. Unused SFR
locations are unimplemented and read as ‘0’s. A list of
SFRs is given in Table 5-3; a full description is provided
in Table 5-5.
(2)
(2)
(2)
(1)
Address
F9Dh
F9Ch
F8Dh
F8Ch
F9Eh
F9Bh
F9Ah
F8Eh
F8Bh
F8Ah
F9Fh
F99h
F98h
F97h
F96h
F95h
F94h
F93h
F92h
F91h
F90h
F8Fh
F89h
F88h
F87h
F86h
F85h
F84h
F83h
F82h
F81h
F80h
MEMCON
OSCTUNE
PORTH
PORTJ
TRISH
TRISJ
PORTG
LATH
PORTF
PORTE
PORTD
PORTC
PORTB
PORTA
LATJ
TRISG
TRISF
TRISE
TRISD
TRISC
TRISB
TRISA
Name
LATG
LATD
LATC
LATF
LATE
LATB
LATA
IPR1
PIR1
PIE1
(3)
(3)
(3)
(3)
(3)
(3)
(4)
Address
F7Dh
F7Ch BAUDCON2
F6Dh
F6Ch
F7Eh BAUDCON1
F7Bh
F7Ah
F6Eh
F6Bh
F6Ah
F7Fh
F79h
F78h
F77h
F76h
F75h
F74h
F73h
F72h
F71h
F70h
F6Fh
F69h
F68h
F67h
F66h
F65h
F64h
F63h
F62h
F61h
F60h
DS39762B-page 79
SSP2CON1
SSP2CON2
ECCP1DEL
ECCP3DEL
ECCP2DEL
CCP4CON
CCP5CON
SSP2STAT
SPBRGH1
SPBRGH2
ECCP3AS
ECCP2AS
SSP2BUF
SSP2ADD
RCREG2
ERDPTH
CCPR4H
CCPR5H
CCPR5L
SPBRG2
TXREG2
ERDPTL
CCPR4L
RCSTA2
TXSTA2
T4CON
EDATA
Name
TMR4
PR4
EIR