PIC18F97J60-I/PF Microchip Technology, PIC18F97J60-I/PF Datasheet - Page 71

• Manufacturer Part Number: PIC18F97J60-I/PF
• Description: IC PIC MCU FLASH 65KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F97J60-I/PF

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Operating Supply Voltage: 2.35 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Package: 100TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 41.667 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100DM163024 - BOARD DEMO PICDEM.NET 2
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.1.3
The 100-pin devices in this family can address up to a
total of 2 Mbytes of program memory. This is achieved
through the external memory bus. There are two
distinct operating modes available to the controllers:
• Microcontroller (MC)
• Extended Microcontroller (EMC)
The program memory mode is determined by setting
the EMB Configuration bits (CONFIG3L<5:4>), as
shown in Register 5-1. (See also Section 24.1
“Configuration Bits” for additional details on the
device Configuration bits.)
The program memory modes operate as follows:
• The Microcontroller Mode accesses only on-chip
REGISTER 5-1:
© 2006 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value when device is unprogrammed
bit 7
bit 6
bit 5-4
bit 3
bit 2-0
Note 1:
Flash memory. Attempts to read above the top of
on-chip memory causes a read of all ‘0’s (a NOP
instruction).
The Microcontroller mode is also the only operating
mode available to 64-pin and 80-pin devices.
R/WO-1
WAIT
(1)
Implemented on 100-pin devices only.
PIC18F9XJ60/9XJ65 PROGRAM
MEMORY MODES
WAIT: External Bus Wait Enable bit
1 = Wait states for operations on external memory bus disabled
0 = Wait states for operations on external memory bus enabled and selected by MEMCON<5:4>
BW: Data Bus Width Select bit
1 = 16-Bit Data Width mode
0 = 8-Bit Data Width mode
EMB1:EMB0: External Memory Bus Configuration bits
11 = Microcontroller mode, external bus disabled
10 = Extended Microcontroller mode,12-Bit Addressing mode
01 = Extended Microcontroller mode,16-Bit Addressing mode
00 = Extended Microcontroller mode, 20-Bit Addressing mode
EASHFT: External Address Bus Shift Enable bit
1 = Address shifting enabled; address on external bus is offset to start at 000000h
0 = Address shifting disabled; address on external bus reflects the PC value
Unimplemented: Read as ‘0’
R/WO-1
BW
CONFIG3L: CONFIGURATION REGISTER 3 LOW
(1)
WO = Write-Once bit
EMB1
R/WO-1
(1)
(1)
EMB0
R/WO-1
Preliminary
(1)
(1)
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
EASHFT
PIC18F97J60 FAMILY
R/WO-1
• The Extended Microcontroller Mode allows
The setting of the EMB Configuration bits also controls
the address bus width of the external memory bus. This
is covered in more detail in Section 7.0 “External
Memory Bus”.
In all modes, the microcontroller has complete access
to data RAM.
Figure 5-3 compares the memory maps of the different
program memory modes. The differences between
on-chip and external memory access limitations are
more fully explained in Table 5-2.
(1)
access to both internal and external program
memories as a single block. The device can
access its entire on-chip program memory. Above
this, the device accesses external program
memory up to the 2-Mbyte program space limit.
Execution automatically switches between the
two memories as required.
(1)
(1)
U-0
—
‘0’ = Bit is cleared
U-0
—
DS39762B-page 69
U-0
—
bit 0