PIC18F97J60-I/PF Microchip Technology, PIC18F97J60-I/PF Datasheet - Page 442

• Manufacturer Part Number: PIC18F97J60-I/PF
• Description: IC PIC MCU FLASH 65KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F97J60-I/PF

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Operating Supply Voltage: 2.35 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Package: 100TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 41.667 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100DM163024 - BOARD DEMO PICDEM.NET 2
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F97J60 FAMILY
TABLE 27-21: I
DS39762B-page 440
100
101
102
103
90
91
106
107
92
109
110
D102
Note 1:
Param.
No.
2:
T
T
T
T
T
T
T
T
T
T
T
C
Symbol
SU
SU
SU
AA
R
HIGH
LOW
F
HD
HD
BUF
B
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCLx to avoid unintended generation of Start or Stop conditions.
A Fast mode I
T
LOW period of the SCLx signal. If such a device does stretch the LOW period of the SCLx signal, it must
output the next data bit to the SDAx line,
T
the SCLx line is released.
SU
R
:
:
:
:
:
STA
DAT
STO
STA
DAT
max. + T
:
DAT
2
Clock High Time
Clock Low Time
SDAx and SCLx Rise
Time
SDAx and SCLx Fall
Time
Start Condition Setup
Time
Start Condition Hold
Time
Data Input Hold Time
Data Input Setup Time
Stop Condition Setup
Time
Output Valid from Clock 100 kHz mode
Bus Free Time
Bus Capacitive Loading
C™ BUS DATA REQUIREMENTS (SLAVE MODE)
250 ns, must then be met. This will automatically be the case if the device does not stretch the
SU
2
:
DAT
C™ bus device can be used in a Standard mode I
= 1000 + 250 = 1250 ns (according to the Standard mode I
Characteristic
100 kHz mode
400 kHz mode
MSSP module
100 kHz mode
400 kHz mode
MSSP module
100 kHz mode
400 kHz mode 20 + 0.1 C
100 kHz mode
400 kHz mode 20 + 0.1 C
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
Preliminary
1.5 T
1.5 T
Min
250
100
4.0
0.6
4.7
1.3
4.7
0.6
4.0
0.6
4.7
0.6
4.7
1.3
—
—
—
—
—
0
0
CY
CY
B
B
1000
3500
Max
300
300
300
0.9
400
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
C bus system, but the requirement,
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
s
s
s
s
s
s
s
s
s
s
s
s
s
© 2006 Microchip Technology Inc.
2
C bus specification), before
PIC18F97J60 family must
operate at a minimum of
1.5 MHz
PIC18F97J60 family must
operate at a minimum of
10 MHz
PIC18F97J60 family must
operate at a minimum of
1.5 MHz
PIC18F97J60 family must
operate at a minimum of
10 MHz
C
10 to 400 pF
C
10 to 400 pF
Only relevant for Repeated
Start condition
After this period, the first
clock pulse is generated
(Note 2)
(Note 1)
Time the bus must be free
before a new transmission
can start
B
B
is specified to be from
is specified to be from
Conditions