PIC18F97J60-I/PF Microchip Technology, PIC18F97J60-I/PF Datasheet - Page 460

• Manufacturer Part Number: PIC18F97J60-I/PF
• Description: IC PIC MCU FLASH 65KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F97J60-I/PF

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Operating Supply Voltage: 2.35 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Package: 100TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 41.667 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100DM163024 - BOARD DEMO PICDEM.NET 2
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F97J60 FAMILY
EUSARTx
Extended Instruction Set
External Clock Input (EC Modes) ....................................... 40
External Memory Bus ....................................................... 105
DS39762B-page 458
Asynchronous Mode ................................................ 309
Baud Rate Generator
Baud Rate Generator (BRG) .................................... 303
Synchronous Master Mode ...................................... 317
Synchronous Slave Mode ........................................ 320
ADDFSR .................................................................. 400
ADDULNK ................................................................ 400
CALLW ..................................................................... 401
MOVSF .................................................................... 401
MOVSS .................................................................... 402
PUSHL ..................................................................... 402
SUBFSR .................................................................. 403
SUBULNK ................................................................ 403
16-Bit Byte Select Mode .......................................... 111
16-Bit Byte Write Mode ............................................ 109
16-Bit Data Width Modes ......................................... 108
16-Bit Mode Timing .................................................. 112
16-Bit Word Write Mode ........................................... 110
21-Bit Addressing ..................................................... 107
8-Bit Data Width Mode ............................................. 113
8-Bit Mode Timing .................................................... 114
Address and Data Line Usage (table) ...................... 107
Address and Data Width .......................................... 107
Address Shifting ....................................................... 107
Control ..................................................................... 106
I/O Port Functions .................................................... 105
Operation in Power-Managed Modes ...................... 115
Program Memory Modes ......................................... 108
Wait States ............................................................... 108
Weak Pull-ups on Port Pins ..................................... 108
Associated Registers, Receive ........................ 313
Associated Registers, Transmit ....................... 311
Auto-Wake-up on Sync Break
Break Character Sequence .............................. 316
Receiver ........................................................... 312
Setting Up 9-Bit Mode with
Transmitter ....................................................... 309
Operation in Power-Managed Modes .............. 303
Associated Registers ....................................... 304
Auto-Baud Rate Detect .................................... 307
Baud Rate Error, Calculating ........................... 304
Baud Rates, Asynchronous Modes .................. 305
High Baud Rate Select (BRGH Bit) .................. 303
Sampling .......................................................... 303
Associated Registers, Receive ........................ 320
Associated Registers, Transmit ....................... 318
Reception ......................................................... 319
Transmission .................................................... 317
Associated Registers, Receive ........................ 322
Associated Registers, Transmit ....................... 321
Reception ......................................................... 321
Transmission .................................................... 320
Extended Microcontroller ................................. 108
Microcontroller ................................................. 108
Character ................................................. 314
Receiving ................................................. 316
Address Detect ........................................ 312
Preliminary
F
Fail-Safe Clock Monitor ........................................... 343, 354
Fast Register Stack ........................................................... 73
Firmware Instructions ...................................................... 357
Flash Configuration Words ........................................ 68, 343
Flash Program Memory ..................................................... 95
FSCM. See Fail-Safe Clock Monitor.
G
GOTO .............................................................................. 378
H
Hardware Multiplier .......................................................... 117
I
I/O Ports ........................................................................... 135
I
2
C Mode (MSSP) ............................................................ 263
and the Watchdog Timer ......................................... 354
Exiting Operation ..................................................... 354
Interrupts in Power-Managed Modes ....................... 355
POR or Wake-up From Sleep .................................. 355
Associated Registers ............................................... 103
Control Registers ....................................................... 96
Erase Sequence ...................................................... 100
Erasing .................................................................... 100
Operation During Code-Protect ............................... 103
Reading ..................................................................... 99
Table Pointer
Table Pointer Boundaries .......................................... 98
Table Reads and Table Writes .................................. 95
Write Sequence ....................................................... 101
Writing ..................................................................... 101
Introduction .............................................................. 117
Operation ................................................................. 117
Performance Comparison ........................................ 117
Pin Capabilities ........................................................ 135
Acknowledge Sequence Timing .............................. 291
Associated Registers ............................................... 297
Baud Rate Generator .............................................. 284
Bus Collision
Clock Arbitration ...................................................... 285
Clock Rate w/BRG ................................................... 284
Clock Stretching ....................................................... 277
Clock Synchronization and the CKP Bit ................... 278
Effects of a Reset .................................................... 292
General Call Address Support ................................. 281
EECON1 and EECON2 ..................................... 96
TABLAT (Table Latch) Register ........................ 98
TBLPTR (Table Pointer) Register ...................... 98
Boundaries Based on Operation ....................... 98
Protection Against Spurious Writes ................. 103
Unexpected Termination ................................. 103
Write Verify ...................................................... 103
During a Repeated Start Condition .................. 295
During a Stop Condition .................................. 296
10-Bit Slave Receive Mode (SEN = 1) ............ 277
10-Bit Slave Transmit Mode ............................ 277
7-Bit Slave Receive Mode (SEN = 1) .............. 277
7-Bit Slave Transmit Mode .............................. 277
© 2006 Microchip Technology Inc.