PIC18F97J60-I/PF Microchip Technology, PIC18F97J60-I/PF Datasheet - Page 231

• Manufacturer Part Number: PIC18F97J60-I/PF
• Description: IC PIC MCU FLASH 65KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F97J60-I/PF

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Operating Supply Voltage: 2.35 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Package: 100TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 41.667 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100DM163024 - BOARD DEMO PICDEM.NET 2
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

18.3.1.4
The LINKIF indicates that the link status has changed.
The actual current link status can be obtained from the
LLSTAT (PHSTAT1<2>) or LSTAT (PHSTAT2<10>) bits
(see Register 18-10 and Register 18-12). Unlike other
interrupt sources, the link status change interrupt is
created in the integrated PHY module; additional steps
must be taken to enable it.
By Reset default, LINKIF is never set for any reason. To
receive it, both the PLNKIE and PGEIE bits must be
set. When the interrupt is enabled, the LINKIF bit will
shadow the contents of the PGIF bit. The PHY only
supports one interrupt, so the PGIF bit will always be
the same as the PLNKIF bit (when both PHY enable
bits are set).
Once LINKIF is set, it can only be cleared in software
or by a Reset. If the link change interrupt is enabled
(LINKIE, PLNKIE, PGEIE and ETHIE are all set), an
interrupt is generated. If the link change interrupt is not
enabled (LINKIE, PLNKIE, PGEIE or ETHIE are
cleared), the user application may poll the PLNKIF flag
and take appropriate action.
The LINKIF bit is read-only. Because reading PHY
registers requires a non-negligible period of time, the
application may instead set PLNKIE and PGEIE, then
poll the LINKIF flag bit. Performing an MII read on the
PHIR register will clear the LINKIF, PGIF and PLNKIF
bits automatically and allow for future link status change
interrupts. See Section 18.2.5 “PHY Registers” for
information on accessing the PHY registers.
18.3.1.5
The DMA interrupt indicates that the DMA module has
completed its memory copy or checksum calculation
(the DMAST bit has transitioned from ‘1’ to ‘0’). Addi-
tionally, this interrupt will be caused if the application
cancels a DMA operation by manually clearing the
DMAST bit. Once set, DMAIF can only be cleared by
the firmware or by a Reset condition. If the DMA inter-
rupt is enabled, an Ethernet interrupt is generated. If
the DMA interrupt is not enabled, the user application
may poll the DMAIF flag status and take appropriate
action. Once processed, the flag bit should be cleared.
18.3.1.6
The receive packet pending interrupt is used to indicate
the presence of one or more data packets in the receive
buffer and to provide a notification means for the arrival
of new packets. When the receive buffer has at least
one packet in it, the PKTIF flag bit is set. In other words,
this interrupt flag will be set any time the Ethernet
Packet Count register (EPKTCNT) is non-zero.
© 2006 Microchip Technology Inc.
Link Change Interrupt (LINKIF)
DMA Interrupt (DMAIF)
Receive Packet Pending Interrupt
(PKTIF)
Preliminary
PIC18F97J60 FAMILY
When the receive packet pending interrupt is enabled
(both PKTIE and ETHIE are set), an Ethernet interrupt
is generated whenever a new packet is successfully
received and written into the receive buffer. If the
receive packet pending interrupt is not enabled (either
PKTIE or ETHIE is cleared), the user application may
poll the PKTIF bit and take appropriate action.
The PKTIF bit can only be cleared indirectly in software,
by decrementing the EPKTCNT register to ‘0’, or by a
Reset condition. See Section 18.5.3 “Receiving Pack-
ets” for more information about clearing the EPKTCNT
register. When the last data packet in the receive buffer
is processed, EPKTCNT becomes zero and the PKTIF
bit is automatically cleared.
18.3.2
The Ethernet interrupt structure implements a version
of Wake-on-LAN, also called Remote Wake-up, using a
Magic Packet data packet. This allows the application
to conserve power in Idle mode, and then return to
full-power operation only when a specific wake-up
packet is received.
For Remote Wake-up to work, the Ethernet module
must remain enabled at all times. It also necessary to
configure the receive filters to select for Magic Packets.
For more information on filter configuration, see
Section 18.8 “Receive Filters”.
To configure the microcontroller for Remote Wake-up:
1.
2.
3.
4.
In this configuration, the receipt of a Magic Packet data
packet will cause a receive packet pending interrupt;
this in turn will cause the microcontroller to wake-up
from the interrupt.
With the Ethernet module enabled and in normal
operating
post-filter
(ERXFCON<5,3> = 1).
Finish processing any pending packets in the
Ethernet buffer.
Enable Ethernet interrupts at the micro-
controller level (PIE2<5> = 1), and the receive
packet pending interrupt at the module level
(EIE<6> = 1).
Place the microcontroller in PRI_IDLE mode
(with the primary clock source selected and
OSCCON<7>
instruction).
ETHERNET INTERRUPTS AND
WAKE-ON-LAN
configuration,
and
=
1,
Magic
execute
enable
DS39762B-page 229
Packets
the
the
SLEEP
CRC
filter