PIC18F97J60-I/PF Microchip Technology, PIC18F97J60-I/PF Datasheet - Page 237

• Manufacturer Part Number: PIC18F97J60-I/PF
• Description: IC PIC MCU FLASH 65KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F97J60-I/PF

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Operating Supply Voltage: 2.35 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Package: 100TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 41.667 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100DM163024 - BOARD DEMO PICDEM.NET 2
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

An example of how the entire assembled transmit
packet looks in memory is shown in Figure 18-9. To
construct and transmit a packet in this fashion:
1.
2.
3.
4.
5.
If a DMA operation was in progress while the TXRTS bit
was set, the module will wait until the DMA operation is
complete before attempting to transmit the packet. This
possible delay is required because the DMA and
FIGURE 18-9:
© 2006 Microchip Technology Inc.
Set the ETXST Pointers to an appropriate
unused location in the buffer. This will be the
location of the per-packet control byte. In the
example, it would be 0120h. It is recommended
that an even address be used for the ETXST
Pointers.
Using EDATA and the EWRPT registers,
sequentially write the packet data to the Ether-
net buffer. In order, write the data for the
per-packet control byte, the destination address,
the source MAC address, the type/length and
the data payload.
Set the ETXND Pointers to point to the last byte
in the data payload. In the example, it would be
programmed to 0156h.
Clear the TXIF flag bit (EIR<3>), and set the
TXIE (EIE<3>) and ETHIE bits to enable an
interrupt when done (if desired).
Start the transmission process by setting the
TXRTS bit (ECON1<3>).
Buffer Pointers
ETXST = 0120h
ETXND = 0156h
SAMPLE TRANSMIT PACKET LAYOUT
Address
016Ah
016Bh
016Ch
016Dh
016Eh
0120h
0121h
0122h
0156h
0157h
0158h
0159h
tsv[23:16]
tsv[31:24]
tsv[39:32]
tsv[47:40]
tsv[55:48]
Memory
tsv[15:8]
data[m]
tsv[7:0]
data[1]
data[2]
0Eh
Preliminary
PIC18F97J60 FAMILY
Status Vector
Data Packet
transmission engine share the same memory arbiter
channel. Similarly, if the DMAST bit is set after TXRTS
is already set, the DMA will wait until the TXRTS bit
becomes clear before doing anything.
While the transmission is in progress, the ETXST and
ETXND Pointers should not be modified. If it is
necessary to cancel the transmission, clear the TXRTS
bit.
When the packet is finished transmitting, or was
aborted due to an error/cancellation, several things
occur:
• The TXRTS bit is cleared.
• A 7-byte transmit status vector is written to the
• The TXIF flag is set
• An interrupt will be generated (if enabled)
• The ETXST and ETXND Pointers will not be
To check if the packet was successfully transmitted,
read the TXABRT bit. If it has been set, poll the BUFER
bit in addition to the various fields in the transmit status
vector to determine the cause. The transmit status
vector is organized as shown in Table 18-4. Multi-byte
fields are written in little-endian format.
Control
buffer at the location pointed to by the ETXND
Pointers + 1.
modified.
Description
PHUGEEN, PPADN,
PCRCEN and POVERRIDE
Destination Address,
Source Address,
Type/Length and Data
Status Vector
Written by the Hardware
Start of the Next Packet
DS39762B-page 235