PIC18F97J60-I/PF Microchip Technology, PIC18F97J60-I/PF Datasheet - Page 43

• Manufacturer Part Number: PIC18F97J60-I/PF
• Description: IC PIC MCU FLASH 65KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F97J60-I/PF

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Operating Supply Voltage: 2.35 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Package: 100TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 41.667 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100DM163024 - BOARD DEMO PICDEM.NET 2
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

2.5
The PIC18F97J60 family of devices includes an internal
oscillator source (INTRC) which provides a nominal
31 kHz output. The INTRC is enabled on device
power-up and clocks the device during its configuration
cycle until it enters operating mode. INTRC is also
enabled if it is selected as the device clock source or if
any of the following are enabled:
• Fail-Safe Clock Monitor
• Watchdog Timer
• Two-Speed Start-up
These features are discussed in greater detail in
Section 24.0 “Special Features of the CPU”.
The INTRC can also be optionally configured as the
default clock source on device start-up by setting the
FOSC2 Configuration bit. This is discussed in
Section 2.7.1 “Oscillator Control Register”.
2.6
Although devices of the PIC18F97J60 family can accept
a wide range of crystals and external oscillator inputs,
they must always have a 25 MHz clock source when
REGISTER 2-1:
© 2006 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3-0
Note 1:
PPST1
R/W-0
Internal Oscillator Block
Ethernet Operation and the
Microcontroller Clock
Available only for ECPLL and HSPLL oscillator configurations; otherwise, this bit is unavailable and is read
as ‘0’.
PPST1: PLL Postscaler Configuration bit
1 = Divide-by-2
0 = Divide-by-3
PLLEN: 5x Frequency Multiplier PLL Enable bit
1 = PLL enabled
0 = PLL disabled
PPST0: PLL Postscaler Enable bit
1 = Postscaler enabled
0 = Postscaler disabled
PPRE: PLL Prescaler Configuration bit
1 = Divide-by-2
0 = Divide-by-3
Unimplemented: Read as ‘0’
PLLEN
R/W-0
OSCTUNE: PLL BLOCK CONTROL REGISTER
(1)
W = Writable bit
‘1’ = Bit is set
PPST0
R/W-0
R/W-0
PPRE
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PIC18F97J60 FAMILY
used for Ethernet applications. No provision is made for
internally generating the required Ethernet clock from a
primary oscillator source of a different frequency. A
frequency tolerance is specified, likely excluding the use
of ceramic resonators. See Section 27.0 “Electrical
Characteristics”, Table 27-6, parameter 5, for more
details.
2.6.1
To accommodate a range of applications and micro-
controller clock speeds, a separate PLL block is
incorporated into the clock system. It consists of three
components:
• A configurable prescaler (1:2 or 1:3)
• A 5x PLL frequency multiplier
• A configurable postscaler (1:1, 1:2, or 1:3)
The operation of the PLL block’s components is
controlled by the OSCTUNE register (Register 2-1).
The use of the PLL block’s prescaler and postscaler,
with or without the PLL itself, provides a range of sys-
tem clock frequencies to choose from, including the
unaltered 25 MHz of the primary oscillator. The full
range of possible oscillator configurations compatible
with Ethernet operation is shown in Table 2-2.
U-0
(1)
—
PLL BLOCK
U-0
—
x = Bit is unknown
U-0
—
DS39762B-page 41
U-0
—
bit 0