PIC18F97J60-I/PF Microchip Technology, PIC18F97J60-I/PF Datasheet - Page 286

• Manufacturer Part Number: PIC18F97J60-I/PF
• Description: IC PIC MCU FLASH 65KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F97J60-I/PF

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Operating Supply Voltage: 2.35 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Package: 100TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 41.667 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100DM163024 - BOARD DEMO PICDEM.NET 2
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F97J60 FAMILY
19.4.7
In I
reload value is placed in the lower 7 bits of the
SSPxADD register (Figure 19-19). When a write
occurs to SSPxBUF, the Baud Rate Generator will
automatically begin counting. The BRG counts down to
0 and stops until another reload has taken place. The
BRG count is decremented twice per instruction cycle
(T
BRG is reloaded automatically.
Once the given operation is complete (i.e., transmis-
sion of the last data bit is followed by ACK), the internal
clock will automatically stop counting and the SCLx pin
will remain in its last state.
Table 19-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPxADD.
FIGURE 19-19:
TABLE 19-3:
DS39762B-page 284
Note 1:
CY
2
C Master mode, the Baud Rate Generator (BRG)
) on the Q2 and Q4 clocks. In I
The I
100 kHz) in all details, but may be used with care where higher rates are required by the application.
BAUD RATE
41.667 MHz
41.667 MHz
20.833 MHz
20.833 MHz
31.25 MHz
31.25 MHz
2
F
C™ interface does not conform to the 400 kHz I
I
OSC
2
C™ CLOCK RATE w/BRG
SSPM3:SSPM0
BAUD RATE GENERATOR BLOCK DIAGRAM
SCLx
2
C Master mode, the
SSPM3:SSPM0
Reload
Control
Preliminary
CLKO
BRG Value
4Dh
19h
67h
13h
09h
33h
Reload
19.4.7.1
Because MSSP1 and MSSP2 are independent, they
can operate simultaneously in I
different baud rates. This is done by using different
BRG reload values for each module.
Because this mode derives its basic clock source from
the system clock, any changes to the clock will affect
both modules in the same proportion. It may be
possible to change one or both baud rates back to a
previous value by changing the BRG reload value.
BRG Down Counter
2
SSPxADD<6:0>
C specification (which applies to rates greater than
Baud Rate and Module
Interdependence
(2 Rollovers of BRG)
© 2006 Microchip Technology Inc.
F
OSC
400 kHz
400 kHz
400 kHz
/4
100 kHz
100 kHz
100 kHz
F
SCL
2
C Master mode at
(1)
(1)
(1)