PIC18F97J60-I/PF Microchip Technology, PIC18F97J60-I/PF Datasheet - Page 293

• Manufacturer Part Number: PIC18F97J60-I/PF
• Description: IC PIC MCU FLASH 65KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F97J60-I/PF

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Operating Supply Voltage: 2.35 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Package: 100TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 41.667 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100DM163024 - BOARD DEMO PICDEM.NET 2
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

19.4.12
An Acknowledge sequence is enabled by setting the
Acknowledge
(SSPxCON2<4>). When this bit is set, the SCLx pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDAx pin. If the user wishes to
generate an Acknowledge, then the ACKDT bit should
be cleared. If not, the user should set the ACKDT bit
before starting an Acknowledge sequence. The Baud
Rate Generator then counts for one rollover period
(T
When the SCLx pin is sampled high (clock arbitration),
the Baud Rate Generator counts for T
is then pulled low. Following this, the ACKEN bit is auto-
matically cleared, the Baud Rate Generator is turned off
and the MSSP module then goes into Idle mode
(Figure 19-25).
19.4.12.1
If the user writes the SSPxBUF when an Acknowledge
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 19-25:
FIGURE 19-26:
© 2006 Microchip Technology Inc.
BRG
) and the SCLx pin is deasserted (pulled high).
ACKNOWLEDGE SEQUENCE
TIMING
WCOL Status Flag
Note: T
SDAx
SCLx
Sequence
Write to SSPxCON2,
SSPxIF
Note: T
Falling edge of
SDAx
SCLx
BRG
9th clock
ACKNOWLEDGE SEQUENCE WAVEFORM
STOP CONDITION RECEIVE OR TRANSMIT MODE
BRG
Acknowledge sequence starts here,
= one Baud Rate Generator period.
ACK
set PEN
= one Baud Rate Generator period.
Enable
the end of receive
ACKEN = 1, ACKDT = 0
SSPxIF set at
write to SSPxCON2
BRG
SDAx asserted low before rising edge of clock
to setup Stop condition
T
T
BRG
. The SCLx pin
BRG
bit,
8
D0
ACKEN
T
SCLx brought high after T
BRG
Preliminary
P
Cleared in
software
T
SCLx = 1 for T
after SDAx sampled high. P bit (SSPxSTAT<4>) is set.
BRG
T
BRG
PIC18F97J60 FAMILY
ACK
19.4.13
A Stop bit is asserted on the SDAx pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN (SSPxCON2<2>). At the end of a
receive/transmit, the SCLx line is held low after the fall-
ing edge of the ninth clock. When the PEN bit is set, the
master will assert the SDAx line low. When the SDAx
line is sampled low, the Baud Rate Generator is
reloaded and counts down to ‘0’. When the Baud Rate
Generator times out, the SCLx pin will be brought high
and one T
later, the SDAx pin will be deasserted. When the SDAx
pin is sampled high while SCLx is high, the P bit
(SSPxSTAT<4>) is set. A T
cleared and the SSPxIF bit is set (Figure 19-26).
19.4.13.1
If the user writes the SSPxBUF when a Stop sequence
is in progress, then the WCOL bit is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
T
PEN bit (SSPxCON2<2>) is cleared by
hardware and the SSPxIF bit is set
BRG
BRG
BRG
9
SSPxIF set at the end
of Acknowledge sequence
, followed by SDAx = 1 for T
BRG
STOP CONDITION TIMING
WCOL Status Flag
ACKEN automatically cleared
(Baud Rate Generator rollover count)
Cleared in
software
BRG
BRG
later, the PEN bit is
DS39762B-page 291