PIC18F97J60-I/PF Microchip Technology, PIC18F97J60-I/PF Datasheet - Page 467

• Manufacturer Part Number: PIC18F97J60-I/PF
• Description: IC PIC MCU FLASH 65KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F97J60-I/PF

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Operating Supply Voltage: 2.35 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Package: 100TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 41.667 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100DM163024 - BOARD DEMO PICDEM.NET 2
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

© 2006 Microchip Technology Inc.
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Master SSP I
Master SSP I
Parallel Slave Port (PSP) Read ............................... 161
Parallel Slave Port (PSP) Write ............................... 160
Program Memory Read ............................................ 430
Program Memory Write ............................................ 431
PWM Auto-Shutdown (P1RSEN = 0,
PWM Auto-Shutdown (P1RSEN = 1,
PWM Direction Change ........................................... 199
PWM Direction Change at Near
PWM Output ............................................................ 186
Repeated Start Condition ......................................... 287
Reset, Watchdog Timer (WDT),
Send Break Character Sequence ............................ 316
Slave Synchronization ............................................. 259
Slow Rise Time (MCLR Tied to V
SPI Mode (Master Mode) ......................................... 258
SPI Mode (Slave Mode, CKE = 0) ........................... 260
SPI Mode (Slave Mode, CKE = 1) ........................... 260
Synchronous Reception
Synchronous Transmission ...................................... 317
Synchronous Transmission (Through TXEN) .......... 318
Time-out Sequence on Power-up
Time-out Sequence on Power-up
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
C Bus Collision During a Repeated
C Bus Collision During a Repeated
C Bus Collision During a Stop
C Bus Collision During a Stop
C Bus Collision During Start
C Bus Collision During Start
C Bus Collision for Transmit and
C Bus Data ............................................................ 439
C Bus Start/Stop Bits ............................................. 439
C Master Mode (7 or 10-Bit Transmission) ........... 289
C Master Mode (7-Bit Reception) .......................... 290
C Slave Mode (10-Bit Reception, SEN = 0) .......... 274
C Slave Mode (10-Bit Reception, SEN = 0,
C Slave Mode (10-Bit Reception, SEN = 1) .......... 280
C Slave Mode (10-Bit Transmission) ..................... 276
C Slave Mode (7-Bit Reception, SEN = 0) ............ 271
C Slave Mode (7-Bit Reception,
C Slave Mode (7-Bit Reception, SEN = 1) ............ 279
C Slave Mode (7-Bit Transmission) ....................... 273
C Slave Mode General Call Address Sequence
C Stop Condition Receive or Transmit Mode ........ 291
Start Condition (Case 1) .................................. 295
Start Condition (Case 2) .................................. 295
Condition (Case 1) ........................................... 296
Condition (Case 2) ........................................... 296
Condition (SCLx = 0) ....................................... 294
Condition (SDAx Only) ..................................... 293
Acknowledge ................................................... 292
ADMSK = 01001) ............................................. 275
SEN = 0, ADMSK = 01011) ............................. 272
(7 or 10-Bit Addressing Mode) ......................... 281
Auto-Restart Disabled) .................................... 202
Auto-Restart Enabled) ..................................... 202
100% Duty Cycle ............................................. 199
Oscillator Start-up Timer (OST) and
Power-up Timer (PWRT) ................................. 432
V
(Master Mode, SREN) ..................................... 319
(MCLR Not Tied to V
(MCLR Not Tied to V
DD
Rise > T
2
2
C Bus Data ........................................ 441
C Bus Start/Stop Bits ........................ 441
PWRT
) ............................................ 57
DD
DD
), Case 1 ....................... 56
), Case 2 ....................... 57
DD
,
Preliminary
PIC18F97J60 FAMILY
Timing Diagrams and Specifications
Top-of-Stack Access .......................................................... 71
TRISE Register
TSTFSZ ........................................................................... 397
Two-Speed Start-up ................................................. 343, 353
Two-Word Instructions
TXSTAx Register
V
V
Voltage Reference Specifications .................................... 424
Voltage Regulator (On-Chip) ........................................... 352
DDCORE
Time-out Sequence on Power-up
Timer0 and Timer1 External Clock .......................... 433
Transition for Entry to Idle Mode ............................... 50
Transition for Entry to SEC_RUN Mode .................... 47
Transition for Entry to Sleep Mode ............................ 49
Transition for Two-Speed Start-up
Transition for Wake From Idle to
Transition for Wake From
Transition From RC_RUN Mode to
Transition From SEC_RUN Mode to
Transition to RC_RUN Mode ..................................... 48
AC Characteristics
Capture/Compare/PWM Requirements
CLKO and I/O Requirements ........................... 429, 430
EUSARTx Synchronous
EUSARTx Synchronous Transmission
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Slave Mode Requirements
External Clock Requirements .................................. 427
I
I
Master SSP I
Master SSP I
Parallel Slave Port Requirements ............................ 434
PLL Clock ................................................................ 428
Program Memory Write Requirements .................... 431
Reset, Watchdog Timer, Oscillator Start-up
Timer0 and Timer1 External
PSPMODE Bit ......................................................... 159
Example Cases ......................................................... 75
BRGH Bit ................................................................. 303
2
2
C Bus Data Requirements (Slave Mode) .............. 440
C Bus Start/Stop Bits
/V
(MCLR Tied to V
(INTRC to HSPLL) ........................................... 353
Run Mode .......................................................... 50
Sleep Mode (HSPLL) ......................................... 49
PRI_RUN Mode ................................................. 48
PRI_RUN Mode (HSPLL) .................................. 47
Internal RC Accuracy ....................................... 428
(Including ECCPx Modules) ............................ 434
Receive Requirements .................................... 443
Requirements .................................................. 443
(Master Mode, CKE = 0) .................................. 435
(Master Mode, CKE = 1) .................................. 436
(Slave Mode, CKE = 0) .................................... 437
(CKE = 1) ......................................................... 438
Requirements (Slave Mode) ............................ 439
Requirements .................................................. 441
Timer, Power-up Timer and Brown-out
Reset Requirements ........................................ 432
Clock Requirements ........................................ 433
CAP
Pin .......................................................... 352
2
2
C Bus Data Requirements ................ 442
C Bus Start/Stop Bits
DD
, V
DD
Rise < T
DS39762B-page 465
PWRT
) ........... 56