PIC18F97J60-I/PF Microchip Technology, PIC18F97J60-I/PF Datasheet - Page 289

• Manufacturer Part Number: PIC18F97J60-I/PF
• Description: IC PIC MCU FLASH 65KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F97J60-I/PF

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Operating Supply Voltage: 2.35 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Package: 100TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 41.667 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100DM163024 - BOARD DEMO PICDEM.NET 2
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

19.4.9
A Repeated Start condition occurs when the RSEN bit
(SSPxCON2<1>) is programmed high and the I
module is in the Idle state. When the RSEN bit is set,
the SCLx pin is asserted low. When the SCLx pin is
sampled low, the Baud Rate Generator is loaded with
the contents of SSPxADD<6:0> and begins counting.
The SDAx pin is released (brought high) for one Baud
Rate Generator count (T
Generator times out, if SDAx is sampled high, the SCLx
pin will be deasserted (brought high). When SCLx is
sampled high, the Baud Rate Generator is reloaded
with the contents of SSPxADD<6:0> and begins count-
ing. SDAx and SCLx must be sampled high for one
T
SDAx pin (SDAx = 0) for one T
Following this, the RSEN bit (SSPxCON2<1>) will be
automatically cleared and the Baud Rate Generator will
not be reloaded, leaving the SDAx pin held low. As
soon as a Start condition is detected on the SDAx and
SCLx pins, the S bit (SSPxSTAT<3>) will be set. The
SSPxIF bit will not be set until the Baud Rate Generator
has timed out.
FIGURE 19-22:
© 2006 Microchip Technology Inc.
BRG
. This action is then followed by assertion of the
Write to SSPxCON2
I
START CONDITION TIMING
2
C MASTER MODE REPEATED
on falling edge of ninth clock,
RSEN bit set by hardware
REPEATED START CONDITION WAVEFORM
BRG
SDAx
SCLx
occurs here:
). When the Baud Rate
BRG
end of Xmit
while SCLx is high.
SDAx = 1,
SCLx (no change)
2
C logic
Preliminary
T
SDAx = 1,
SCLx = 1
BRG
PIC18F97J60 FAMILY
Immediately following the SSPxIF bit getting set, the user
may write the SSPxBUF with the 7-bit address in 7-bit
mode or the default first address in 10-bit mode. After the
first eight bits are transmitted and an ACK is received, the
user may then transmit an additional eight bits of address
(10-bit mode) or eight bits of data (7-bit mode).
19.4.9.1
If the user writes the SSPxBUF when a Repeated Start
sequence is in progress, the WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
T
Note:
BRG
Note 1: If RSEN is programmed while any other
Sr = Repeated Start
2: A bus collision during the Repeated Start
T
BRG
Because queueing of events is not
allowed, writing of the lower 5 bits of
SSPxCON2 is disabled until the Repeated
Start condition is complete.
event is in progress, it will not take effect.
condition occurs if:
• SDAx is sampled low when SCLx
• SCLx goes low before SDAx is
WCOL Status Flag
At completion of Start bit,
hardware clears RSEN bit
goes from low-to-high.
asserted low. This may indicate that
another master is attempting to
transmit a data ‘1’.
S bit set by hardware
and sets SSPxIF
Write to SSPxBUF occurs here
T
BRG
1st bit
T
BRG
DS39762B-page 287