PIC18F97J60-I/PF Microchip Technology, PIC18F97J60-I/PF Datasheet - Page 217

• Manufacturer Part Number: PIC18F97J60-I/PF
• Description: IC PIC MCU FLASH 65KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F97J60-I/PF

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Operating Supply Voltage: 2.35 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Package: 100TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 41.667 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100DM163024 - BOARD DEMO PICDEM.NET 2
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

REGISTER 18-5:
© 2006 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-5
bit 4
bit 3
bit 2
bit 1
bit 0
PADCFG2
R/W-0
PADCFG2:PADCFG0: Automatic Pad and CRC Configuration bits
111 = All short frames are zero-padded to 64 bytes and a valid CRC will then be appended
110 = No automatic padding of short frames
101 = MAC automatically detects VLAN protocol frames which have a 8100h type field and auto-
100 = No automatic padding of short frames
011 = All short frames are zero-padded to 64 bytes and a valid CRC is appended
010 = No automatic padding of short frames
001 = All short frames are zero-padded to 60 bytes and a valid CRC is appended
000 = No automatic padding of short frames
TXCRCEN: Transmit CRC Enable bit
1 = MAC apends a valid CRC to all frames transmitted regardless of the PADCFG<2:0> bits.
0 = MAC does not append a CRC. The last 4 bytes are checked and if it is an invalid CRC, it is
PHDREN: Proprietary Header Enable bit
1 = Frames presented to the MAC contain a 4-byte proprietary header which is not used when
0 = No proprietary header is present. The CRC covers all data (normal operation).
HFRMEN: Huge Frame Enable bit
1 = Jumbo frames and frames of any illegal size are allowed to be transmitted and receieved
0 = Frames bigger than MAMXFL are truncated when transmitted or received
FRMLNEN: Frame Length Checking Enable bit
1 = The type/length field of transmitted and received frames is checked. If it represents a length, the
0 = Frame lengths are not compared with the type/length field
FULDPX: MAC Full-Duplex Enable bit
1 = MAC operates in Full-Duplex mode, application must also set PDPXMD (PHCON1<8>)
0 = MAC operates in Half-Duplex mode, application must also clear PDPXMD
PADCFG1
R/W-0
TXCRCEN must be set if the PADCFG bits specify that a valid CRC is appended.
reported in the transmit status vector.
calculating the CRC
frame size is compared and mismatches are reported in the transmit/receive status vector.
MACON3: MAC CONTROL REGISTER 3
matically pad to 64 bytes. If the frame is not a VLAN frame, it is padded to 60 bytes. After padding,
a valid CRC is appended.
W = Writable bit
‘1’ = Bit is set
PADCFG0
R/W-0
TXCRCEN
R/W-0
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PHDREN
PIC18F97J60 FAMILY
R/W-0
HFRMEN
R/W-0
x = Bit is unknown
FRMLNEN
R/W-0
DS39762B-page 215
FULDPX
R/W-0
bit 0