PIC18F97J60-I/PF Microchip Technology, PIC18F97J60-I/PF Datasheet - Page 299

• Manufacturer Part Number: PIC18F97J60-I/PF
• Description: IC PIC MCU FLASH 65KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F97J60-I/PF

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Operating Supply Voltage: 2.35 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Package: 100TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 41.667 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100DM163024 - BOARD DEMO PICDEM.NET 2
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TABLE 19-4:
© 2006 Microchip Technology Inc.
INTCON
PIR1
PIE1
IPR1
PIR2
PIE2
IPR2
PIR3
PIE3
IPR3
TRISC
TRISD
SSP1BUF
SSP1ADD
SSP1CON1
SSP1CON2
SSP1STAT
SSP2BUF
SSP2ADD
SSP2CON1
SSP2CON2
SSP2STAT
Legend:
Note 1:
Name
2:
— = unimplemented, read as ‘0’, r = reserved. Shaded cells are not used by the MSSP module in I
These bits are only available in 100-pin devices; otherwise, they are unimplemented and read as ‘0’.
Alternate bit definitions in I
MSSP1 Receive Buffer/Transmit Register
MSSP2 Receive Buffer/Transmit Register
MSSP1 Address Register (I
MSSP2 Address Register (I
GIE/GIEH PEIE/GIEL
SSP2IE
SSP2IP
SSP2IF
OSCFIF
OSCFIE
OSCFIP
TRISC7
TRISD7
WCOL
WCOL
PSPIF
PSPIE
PSPIP
GCEN
GCEN
GCEN
GCEN
Bit 7
SMP
SMP
REGISTERS ASSOCIATED WITH I
(1)
(1)
(1)
TRISD6
ACKSTAT
ACKSTAT ADMSK5
ACKSTAT
ACKSTAT ADMSK5
BCL2IF
BCL2IE
BCL2IP
TRISC6
SSPOV
SSPOV
CMIE
CMIP
ADIE
ADIP
CMIF
ADIF
Bit 6
CKE
CKE
(1)
(1)
(1)
(1)
2
C™ Slave mode.
TRISD5
2
2
TMR0IE
TRISC5
SSPEN
ACKDT
SSPEN
ACKDT
C™ Slave mode), MSSP1 Baud Rate Reload Register (I
C Slave mode), MSSP2 Baud Rate Reload Register (I
RC1IF
RC1IE
RC1IP
ETHIF
ETHIE
ETHIP
RC2IF
RC2IE
RC2IP
Bit 5
D/A
D/A
(1)
(2)
(2)
ADMSK4
ADMSK4
Preliminary
TRISC4
TRISD4
ACKEN
ACKEN
INT0IE
TX1IF
TX1IE
TX1IP
TX2IF
TX2IE
TX2IP
Bit 4
CKP
CKP
P
P
r
r
r
(2)
(2)
2
C™ OPERATION
PIC18F97J60 FAMILY
ADMSK3
ADMSK3
TMR4IF
TMR4IE
TMR4IP
SSP1IF
SSP1IE
SSP1IP
BCL1IE
BCL1IP
TRISC3
TRISD3
BCL1IF
SSPM3
SSPM3
RCEN
RCEN
RBIE
Bit 3
S
S
(2)
(2)
ADMSK2
ADMSK2
TMR0IF
CCP1IF
CCP1IE
CCP1IP
CCP5IF
CCP5IE
CCP5IP
TRISC2
TRISD2
SSPM2
SSPM2
Bit 2
PEN
PEN
R/W
R/W
—
—
—
(2)
(2)
ADMSK1
ADMSK1
TMR2IF
TMR2IE
TMR2IP
TMR3IF
TMR3IE
TMR3IP
CCP4IF
CCP4IE
CCP4IP
TRISC1
TRISD1
SSPM1
SSPM1
INT0IF
RSEN
RSEN
Bit 1
2
UA
UA
C Master mode)
2
C Master mode)
(2)
(2)
TMR1IF
TMR1IE
TMR1IP
CCP2IE
CCP2IP
CCP3IE
CCP3IP
CCP2IF
CCP3IF
TRISC0
TRISD0
SSPM0
SSPM0
DS39762B-page 297
Bit 0
RBIF
SEN
SEN
SEN
SEN
BF
BF
2
C™ mode.
on Page:
Values
Reset
59
61
61
61
61
61
61
61
61
61
61
61
60
63
60
60
60
60
63
63
63
63