PIC18F97J60-I/PF Microchip Technology, PIC18F97J60-I/PF Datasheet - Page 138

• Manufacturer Part Number: PIC18F97J60-I/PF
• Description: IC PIC MCU FLASH 65KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F97J60-I/PF

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Operating Supply Voltage: 2.35 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Package: 100TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 41.667 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100DM163024 - BOARD DEMO PICDEM.NET 2
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F97J60 FAMILY
10.1.2
The voltage tolerance of pins used as device inputs is
dependent on the pin’s input function. Pins that are used
as digital only inputs are able to handle DC voltages up
to 5.5V, a level typical for digital logic circuits. In contrast,
pins that also have analog input functions of any kind
can only tolerate voltages up to V
beyond V
Table 10-2 summarizes the input capabilities. Refer to
Section 27.0 “Electrical Characteristics” for more
details.
TABLE 10-2:
10.2
PORTA is a 6-bit wide, bidirectional port; it is fully
implemented on all devices. The corresponding Data
Direction register is TRISA. Setting a TRISA bit (= 1)
will make the corresponding PORTA pin an input (i.e.,
put
high-impedance mode). Clearing a TRISA bit (= 0) will
make the corresponding PORTA pin an output (i.e., put
the contents of the output latch on the selected pin).
Reading the PORTA register reads the status of the
pins, whereas writing to it, will write to the port latch.
The Output Latch register (LATA) is also memory
mapped. Read-modify-write operations on the LATA
register read and write the latched output value for
PORTA.
DS39762B-page 136
PORTA<5:0>
PORTF<6:1>
PORTH<7:4>
PORTB<7:0>
PORTC<7:0>
PORTD<7:0>
PORTE<7:0>
PORTF<7>
PORTG<7:0>
PORTH<3:0>
PORTJ<7:0>
Note 1:
Port or Pin
the
2:
PORTA, TRISA and
LATA Registers
DD
Partially implemented on 64-pin and
80-pin devices; fully implemented on
100-pin devices.
Unavailable on 64-pin devices.
INPUT PINS AND VOLTAGE
CONSIDERATIONS
corresponding
on these pins are always to be avoided.
(2)
(1)
(2)
(1)
(2)
(1)
INPUT VOLTAGE LEVELS
Tolerated
Input
5.5V
V
DD
output
Only V
tolerated.
Tolerates input levels
above V
most standard logic.
DD
. Voltage excursions
Description
DD
DD
driver
input levels
, useful for
in
Preliminary
a
The RA4 pin is multiplexed with the Timer0 module
clock input to become the RA4/T0CKI pin. The other
PORTA pins are multiplexed with the analog V
and V
A/D converter inputs is selected by clearing or setting
the PCFG3:PCFG0 control bits in the ADCON1
register.
The RA4/T0CKI pin is a Schmitt Trigger input. All other
PORTA pins have TTL input levels and full CMOS
output drivers.
The TRISA register controls the direction of the PORTA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
The RA0 and RA1 pins can also be configured as the
outputs for the two Ethernet LED indicators. When
configured, these two pins are the only pins on PORTA
that are capable of high output drive levels.
Although the port is only six bits wide, PORTA<7> is
implemented as RJPU, the weak pull-up control bit for
PORTJ. In a similar fashion, the LATA<7:6> bits are
implemented, not as latch bits, but the pull-up control
bits, RDPU and REPU, for PORTD and PORTE.
Setting these bits enables the pull-ups for the corre-
sponding port. Because their port pins are not used, the
TRISA<7:6> bits are not implemented.
EXAMPLE 10-1:
CLRF
CLRF
MOVLW
MOVWF
MOVWF
MOVWF
MOVLW
MOVWF
Note:
REF
- inputs. The operation of pins RA5:RA0 as
PORTA
LATA
07h
ADCON1 ; for digital inputs
07h
CMCON
0CFh
TRISA
RA5 and RA3:RA0 are configured as
analog inputs on any Reset and are read
as ‘0’. RA4 is configured as a digital input.
; Initialize PORTA by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Configure A/D
; Configure comparators
; for digital input
; Value used to
; initialize data
; direction
; Set RA<3:0> as inputs
; RA<5:4> as outputs
INITIALIZING PORTA
© 2006 Microchip Technology Inc.
REF
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