PIC18F97J60-I/PF Microchip Technology, PIC18F97J60-I/PF Datasheet - Page 332

• Manufacturer Part Number: PIC18F97J60-I/PF
• Description: IC PIC MCU FLASH 65KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F97J60-I/PF

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Operating Supply Voltage: 2.35 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Package: 100TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 41.667 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100DM163024 - BOARD DEMO PICDEM.NET 2
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F97J60 FAMILY
21.5
Figure 21-3 shows the operation of the A/D converter
after the GO/DONE bit has been set and the
ACQT2:ACQT0 bits are cleared. A conversion is
started after the following instruction to allow entry into
Sleep mode before the conversion begins.
Figure 21-4 shows the operation of the A/D converter
after the GO/DONE bit has been set, the ACQT2:ACQT0
bits are set to ‘010’ and a 4 T
selected before the conversion starts.
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The A/D Result register
pair will NOT be updated with the partially completed
A/D
ADRESH:ADRESL registers will continue to contain
the value of the last completed conversion (or the last
value written to the ADRESH:ADRESL registers).
After the A/D conversion is completed or aborted, a
2 T
started. After this wait, acquisition on the selected
channel is automatically started.
FIGURE 21-3:
FIGURE 21-4:
DS39762B-page 330
Note:
Set GO/DONE bit
(Holding capacitor continues
acquiring input)
AD
1
wait is required before the next acquisition can be
T
CY
conversion
Set GO/DONE bit
Holding capacitor is disconnected from analog input (typically 100 ns)
A/D Conversions
T
– T
ACQT
Acquisition
Automatic
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
2
AD
Time
Conversion starts
T
Cycles
AD
3
1 T
sample.
A/D CONVERSION T
A/D CONVERSION T
AD
b9
4
2 T
AD
Conversion starts
(Holding capacitor is disconnected)
acquisition time has been
AD
b8
1
This
3 T
AD
b7
b9
Next Q4: ADRESH/ADRESL is loaded, GO/DONE bit is cleared,
2
4 T
means
Next Q4: ADRESH:ADRESL is loaded, GO/DONE bit is cleared,
AD
b6
b8
3
AD
AD
5 T
ADIF bit is set, holding capacitor is connected to analog input.
CYCLES (ACQT2:ACQT0 = 000, T
CYCLES (ACQT2:ACQT0 = 010, T
Preliminary
ADIF bit is set, holding capacitor is reconnected to analog input.
AD
the
b5
b7
4
6 T
AD
b4
T
b6
5
AD
7 T
Cycles
21.6
An A/D conversion can be started by the “Special Event
Trigger” of the ECCP2 module. This requires that the
CCP2M3:CCP2M0
programmed as ‘1011’ and that the A/D module is
enabled (ADON bit is set). When the trigger occurs, the
GO/DONE bit will be set, starting the A/D acquisition
and conversion and the Timer1 (or Timer3) counter will
be reset to zero. Timer1 (or Timer3) is reset to auto-
matically repeat the A/D acquisition period with minimal
software overhead (moving ADRESH/ADRESL to the
desired location). The appropriate analog input
channel must be selected and the minimum acquisition
period is either timed by the user, or an appropriate
T
sets the GO/DONE bit (starts a conversion).
If the A/D module is not enabled (ADON is cleared), the
Special Event Trigger will be ignored by the A/D
module but will still reset the Timer1 (or Timer3)
counter.
AD
ACQ
b3
b5
6
8
time is selected before the Special Event Trigger
T
AD
b2
Use of the ECCP2 Trigger
b4
7
9 T
AD
b1
b3
10
8
T
AD
b0
bits
b2
9
11
© 2006 Microchip Technology Inc.
ACQ
ACQ
10
b1
(CCP2CON<3:0>)
= 0)
= 4 T
11
b0
AD
)
be