PIC18F97J60-I/PF Microchip Technology, PIC18F97J60-I/PF Datasheet - Page 258

• Manufacturer Part Number: PIC18F97J60-I/PF
• Description: IC PIC MCU FLASH 65KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F97J60-I/PF

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Operating Supply Voltage: 2.35 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Package: 100TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 41.667 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100DM163024 - BOARD DEMO PICDEM.NET 2
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F97J60 FAMILY
19.3.2
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits (SSPxCON1<5:0> and SSPxSTAT<7:6>).
These control bits allow the following to be specified:
• Master mode (SCKx is the clock output)
• Slave mode (SCKx is the clock input)
• Clock Polarity (Idle state of SCKx)
• Data Input Sample Phase (middle or end of data
• Clock Edge (output data on rising/falling edge of
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
Each MSSP module consists of a transmit/receive shift
register (SSPxSR) and a buffer register (SSPxBUF).
The SSPxSR shifts the data in and out of the device,
MSb first. The SSPxBUF holds the data that was
written to the SSPxSR until the received data is ready.
Once the 8 bits of data have been received, that byte is
moved to the SSPxBUF register. Then, the Buffer Full
detect bit, BF (SSPxSTAT<0>), and the interrupt flag
bit, SSPxIF, are set. This double-buffering of the
received data (SSPxBUF) allows the next byte to start
reception before reading the data that was just
EXAMPLE 19-1:
DS39762B-page 256
LOOP
output time)
SCKx)
BTFSS
BRA
MOVF
MOVWF
MOVF
MOVWF
OPERATION
SSP1STAT, BF
LOOP
SSP1BUF, W
RXDATA
TXDATA, W
SSP1BUF
LOADING THE SSP1BUF (SSP1SR) REGISTER
;Has data been received (transmit complete)?
;No
;WREG reg = contents of SSP1BUF
;Save in user RAM, if data is meaningful
;W reg = contents of TXDATA
;New data to xmit
Preliminary
written. If the interrupt method is not going to be used,
loading
received. Any write to the SSPxBUF register during
transmission/reception of data will be ignored and the
Write Collision detect bit, WCOL (SSPxCON1<7>), will
be set. User software must clear the WCOL bit so that
it can be determined if the following write(s) to the
SSPxBUF register completed successfully.
When the application software is expecting to receive
valid data, the SSPxBUF should be read before the next
byte of data to transfer is written to the SSPxBUF. The
Buffer Full bit, BF (SSPxSTAT<0>), indicates when
SSPxBUF has been loaded with the received data
(transmission is complete). When the SSPxBUF is read,
the BF bit is cleared. This data may be irrelevant if the
SPI is only a transmitter. Generally, the MSSP interrupt
is used to determine when the transmission/reception
has completed. The SSPxBUF must be read and/or
then software polling can be done to ensure that a write
collision does not occur. Example 19-1 shows the
transmission.
The SSPxSR is not directly readable or writable and
can only be accessed by addressing the SSPxBUF
register. Additionally, the SSPxSTAT register indicates
the various status conditions.
of
the
SSP1BUF
© 2006 Microchip Technology Inc.
(SSP1SR)
for
data