PIC18F97J60-I/PF Microchip Technology, PIC18F97J60-I/PF Datasheet - Page 433

IC PIC MCU FLASH 65KX16 100TQFP

PIC18F97J60-I/PF

Manufacturer Part Number
PIC18F97J60-I/PF
Description
IC PIC MCU FLASH 65KX16 100TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18F97J60-I/PF

Program Memory Type
FLASH
Program Memory Size
128KB (64K x 16)
Package / Case
100-TQFP, 100-VQFP
Core Processor
PIC
Core Size
8-Bit
Speed
41.667MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
70
Ram Size
3808 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3808 B
Interface Type
Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
Maximum Clock Frequency
41.667 MHz
Number Of Programmable I/os
70
Number Of Timers
5
Operating Supply Voltage
2.35 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
Package
100TQFP
Device Core
PIC
Family Name
PIC18
Maximum Speed
41.667 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162064 - HEADER INTFC MPLABICD2 64/80/100DM163024 - BOARD DEMO PICDEM.NET 2
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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PIC18F97J60-I/PF
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FIGURE 27-7:
TABLE 27-11: PROGRAM MEMORY WRITE TIMING REQUIREMENTS
© 2006 Microchip Technology Inc.
150
151
153
154
156
157
157A
166
171
171A
Param.
Operating Conditions: 2.0V < V
AD<15:0>
A<19:16>
No
WRH or
OSC1
UB or
WRL
BA0
ALE
CE
LB
TadV2alL
TalL2adl
TwrH2adl WRn
TwrL
TadV2wrH Data Valid before WRn
TbsV2wrL Byte Select Valid before WRn
TwrH2bsI
TalH2alH
TalH2csL
TubL2oeH AD Valid to Chip Enable Active
Symbol
Address Out Valid to ALE
ALE
WRn Pulse Width
(byte select setup time)
WRn
ALE
Chip Enable Active to ALE
171A
PROGRAM MEMORY WRITE TIMING DIAGRAM
Q1
to Address Out Invalid (address hold time)
to ALE
to Data Out Invalid (data hold time)
to Byte Select Invalid (byte select hold time)
CC
Address
< 3.6V, -40°C < T
150
151
171
(cycle time)
Q2
Characteristics
157
(data setup time)
A
(address setup time)
< +125°C unless otherwise stated.
Preliminary
Q3
Address
166
PIC18F97J60 FAMILY
Data
154
156
Q4
153
0.25 T
0.125 T
0.25 T
0.5 T
0.5 T
0.25 T
Min
CY
CY
CY
CY
5
5
CY
– 10
CY
– 10
– 5
– 20
– 5
157A
Q1
0.25 T
0.5 T
Typ
CY
CY
DS39762B-page 431
Address
Address
Max
10
Q2
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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