PIC18F97J60-I/PF Microchip Technology, PIC18F97J60-I/PF Datasheet - Page 230

• Manufacturer Part Number: PIC18F97J60-I/PF
• Description: IC PIC MCU FLASH 65KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F97J60-I/PF

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Operating Supply Voltage: 2.35 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Package: 100TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 41.667 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100DM163024 - BOARD DEMO PICDEM.NET 2
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F97J60 FAMILY
18.3.1.1
The receive error interrupt is used to indicate that a
packet being received was aborted due to an error
condition. Three errors are possible:
1.
2.
3.
When a packet is being received and the receive error
occurs, the packet being received will be aborted (per-
manently lost) and the RXERIF bit will be set to ‘1’.
Once set, RXERIF can only be cleared by firmware or
by a Reset condition. If the receive error interrupt and
Ethernet interrupt are enabled (both RXERIE and
ETHIE are set), an Ethernet interrupt is generated. If
the receive error interrupt is not enabled (either
RXERIE or ETHIE are cleared), the application may
poll RXERIF and take appropriate action.
Normally, upon the first two receive error conditions
(buffer overflow or potential EPKTCNT overflow), the
application would process any packets pending from
the receive buffer and then make additional room for
future packets by advancing the ERXRDPT registers
(low byte first) and decrementing the EPKTCNT regis-
ter. See Section 18.5.3.3 “Freeing Receive Buffer
Space” for more information on processing packets.
Once processed, the application should clear the
RXERIF bit.
The third condition (insufficient RX memory bandwidth)
can be identified by checking if the BUFER bit
(ESTAT<6>) has been set. Memory access errors that
set BUFER are generally transient in nature, and do not
require run-time resolution. Adjustments to the applica-
tion and its allocation of buffer memory bandwidth may
be necessary if BUFER errors are frequent or
persistent.
18.3.1.2
The transmit error interrupt is used to indicate that a
transmit abort has occurred. An abort can occur
because of any of the following conditions:
1.
2.
3.
DS39762B-page 228
No buffer space is available to store the
incoming packet (buffer overflow);
Receiving another packet would cause the
EPKTCNT counter to overflow, because it
already contains the value 255; or
The Ethernet RX hardware was not allocated
enough memory bandwidth to write the
incoming data to the buffer.
More than 15 collisions occurred while attempting
to transmit a given packet.
A late collision (collision after 64 bytes of a
packet had been transmitted) has occurred.
The transmission was unable to gain an oppor-
tunity to transmit the packet because the
medium was constantly occupied for too long.
The deferral limit was reached and the DEFER
bit (MACON4<6>) was clear.
Receive Error Interrupt (RXERIF)
Transmit Error Interrupt (TXERIF)
Preliminary
4.
5.
Upon any of these conditions, the TXERIF flag is set to
‘1’. Once set, it can only be cleared by firmware or by a
Reset condition. If the transmit error interrupt is
enabled (TXERIE and ETHIE are both set), an Ethernet
interrupt is generated. If the transmit error interrupt is
not enabled (either TXERIE or ETHIE is cleared), the
application may poll TXERIF and take appropriate
action. Once the interrupt is processed, the flag bit
should be cleared.
After a transmit abort, the TXRTS bit (ECON1<3>) will
be cleared, the TXABRT bit (ESTAT<1>) becomes set
and the transmit status vector will be written at the
ETXND registers + 1. The MAC will not automatically
attempt to retransmit the packet. The application may
wish to read the transmit status vector and BUFER bit
to determine the cause of the abort. After determining
the problem and solution, the application should clear
the BUFER (if set) and TXABRT bits so that future
aborts can be detected accurately.
In Full-Duplex mode, conditions 4 and 5 are the only
ones that should cause this interrupt. Condition 5 can
be further distinguished as it also sets the BUFER bit.
Collisions and other problems related to sharing the
network are not possible on full-duplex networks. The
conditions which cause the transmit error interrupt
meet the requirements of the transmit interrupt. As a
result, when this interrupt occurs, TXIF will also be
simultaneously set.
18.3.1.3
The transmit interrupt is used to indicate that the
requested packet transmission has ended (the TXRTS
bit has transitioned from ‘1’ to ‘0’). Upon transmission
completion, abort, or transmission cancellation by the
application, the TXIF flag will be set to ‘1’. If the
application did not clear the TXRTS bit, and the
TXABRT bit is not set, the packet was successfully
transmitted. Once TXIF is set, it can only be cleared in
software or by a Reset condition. If the transmit
interrupt is enabled (TXIE and ETHIE are both set), an
interrupt is generated. If the transmit interrupt is not
enabled (either TXIE or ETHIE is cleared), the
application may poll the TXIF bit and take appropriate
action.
An attempt to transmit a packet larger than the
maximum frame length defined by the MAMXFL
registers
HFRMEN bit (MACON3<2>) or per-packet
POVERRIDE and PHUGEEN bits.
The Ethernet buffer did not have enough mem-
ory bandwidth to maintain the required 10 Mbit/s
transfer rate (buffer underrun).
Transmit Interrupt (TXIF)
was
made
© 2006 Microchip Technology Inc.
without
setting
the