PIC18F97J60-I/PF Microchip Technology, PIC18F97J60-I/PF Datasheet - Page 163

• Manufacturer Part Number: PIC18F97J60-I/PF
• Description: IC PIC MCU FLASH 65KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F97J60-I/PF

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Operating Supply Voltage: 2.35 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Package: 100TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 41.667 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100DM163024 - BOARD DEMO PICDEM.NET 2
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

FIGURE 10-4:
TABLE 10-21: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
© 2006 Microchip Technology Inc.
PORTD
LATD
TRISD
PORTE
LATE
TRISE
PSPCON
INTCON
PIR1
PIE1
IPR1
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port.
Name
PORTD<7:0>
PSPIF
GIE/GIEH PEIE/GIEL TMR0IE
OBF
TRISD7
TRISE7
LATD7
LATE7
PSPIE
PSPIP
WR
PSPIF
IBF
RD
CS
Bit 7
RD7
RE7
IBF
PARALLEL SLAVE PORT READ WAVEFORMS
Q1
TRISD6
TRISE6
LATD6
LATE6
ADIE
ADIP
ADIF
Bit 6
OBF
RD6
RE6
Q2
TRISD5
TRISE5
LATD5
LATE5
RC1IE
RC1IP
RC1IF
IBOV
Bit 5
RD5
RE5
Q3
Q4
PSPMODE
TRISD4
TRISE4
INT0IE
LATD4
LATE4
Preliminary
TX1IF
TX1IE
TX1IP
Bit 4
RD4
RE4
Q1
PIC18F97J60 FAMILY
TRISD3
TRISE3
SSP1IE
SSP1IP
SSP1IF
Q2
LATD3
LATE3
RBIE
Bit 3
RD3
RE3
—
Q3
TRISD2
TMR0IF
CCP1IF
CCP1IE
CCP1IP
TRISE2
LATD2
LATE2
Bit 2
RD2
RE2
—
Q4
TMR2IF
TMR2IE
TMR2IP
TRISD1
TRISE1
Q1
LATD1
INT0IF
LATE1
Bit 1
RD1
RE1
—
Q2
TMR1IE
TMR1IP
TRISD0
TMR1IF
TRISE0
LATD0
LATE0
DS39762B-page 161
RBIF
Bit 0
RD0
RE0
—
Q3
on Page:
Values
Reset
Q4
62
62
61
62
62
61
61
59
61
61
61