PIC18F97J60-I/PF Microchip Technology, PIC18F97J60-I/PF Datasheet - Page 347

• Manufacturer Part Number: PIC18F97J60-I/PF
• Description: IC PIC MCU FLASH 65KX16 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F97J60-I/PF

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Operating Supply Voltage: 2.35 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Package: 100TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 41.667 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100DM163024 - BOARD DEMO PICDEM.NET 2
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

REGISTER 24-1:
REGISTER 24-2:
© 2006 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value when device is unprogrammed
bit 7
bit 6
bit 5
bit 4-1
bit 0
bit 7
Legend:
R = Readable bit
-n = Value when device is unprogrammed
bit 7-3
bit 2
bit 1-0
Note 1:
R/WO-1
DEBUG
—
U-0
2:
(2)
This bit should always be maintained as ‘0’.
The value of these bits in program memory should always be ‘1’. This ensures that the location is
executed as a NOP if it is accidentally executed.
DEBUG: Background Debugger Enable bit
1 = Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins
0 = Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug
XINST: Extended Instruction Set Enable bit
1 = Instruction set extension and Indexed Addressing mode enabled
0 = Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
STVREN: Stack Overflow/Underflow Reset Enable bit
1 = Reset on stack overflow/underflow enabled
0 = Reset on stack overflow/underflow disabled
Unimplemented: Read as ‘0’
WDTEN: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled (control is placed on SWDTEN bit)
Unimplemented: Read as ‘0’
CP0: Code Protection bit
1 = Program memory is not code-protected
0 = Program memory is code-protected
Unimplemented: Read as ‘0’
R/WO-1
XINST
—
U-0
(2)
CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h)
CONFIG1L: CONFIGURATION REGISTER 1 LOW (BYTE ADDRESS 300000h)
WO = Write-Once bit
WO = Write-Once bit
STVREN
R/WO-0
—
U-0
(2)
—
U-0
U-0
—
Preliminary
(2)
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
PIC18F97J60 FAMILY
U-0
U-0
—
—
(1)
R/WO-1
CP0
U-0
—
‘0’ = Bit is cleared
‘0’ = Bit is cleared
U-0
U-0
—
—
DS39762B-page 345
WDTEN
R/WO-1
U-0
—
bit 0
bit 0