EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 116

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

DSP Block Resource Descriptions
5–16
Stratix III Device Handbook, Volume 1
compile time. The first-stage adders are used by the sum modes to
compute the sum of two multipliers, 18 × 18-complex multipliers, and to
perform the first stage of a 36 × 36 multiply and shift operation.
Depending on your specifications, the output of the first-stage adder has
the option to feed into the pipeline registers, second-stage adder, round
and saturation unit, or the output registers.
Pipeline Register Stage
The output from the first-stage adder can either feed or bypass the
pipeline registers, as shown in
DSP block’s maximum performance (at the expense of extra cycles of
latency), especially when using the subsequent DSP block stages. Pipeline
registers split up the long signal path between the
input-registers/multiplier/first-stage adder and the second-stage
adder/round-and-saturation/output-registers, creating two shorter
paths.
Second-Stage Adder
There are four individual 44-bit second-stage adders per DSP block
(2 adders per half DSP block). You can configure the second-stage adders
as follows:
■
■
■
■
1
The output of the second-stage adder has the option to go into the round
and saturation logic unit or the output register.
1
The final stage of a 36-bit multiplier
A sum of four (18 × 18)
An accumulator (44-bits maximum)
A chained output summation (44-bits maximum)
The chained-output adder can be used at the same time as a
second-level adder in chained output summation mode.
You cannot use the second-stage adder independently from the
multiplier and first-stage adder.
Figure
5–6. Pipeline registers increase the
Altera Corporation
October 2007