EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 323

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Differential
Receiver
Altera Corporation
November 2007
The Stratix III device has dedicated circuitry to receive high-speed
differential signals.
The receiver has a differential buffer, a shared PLL_Lx/PLL_Rx, dynamic
phase alignment (DPA) block, synchronization FIFO buffer, Data
realignment block, and a deserializer. The differential buffer can receive
LVDS, mini-LVDS, and RSDS signal levels, which are statically set in the
Quartus II software assignment editor. The PLL receives the external
source clock input that is transmitted with the data and generates
different phases of the same clock. The DPA block chooses one of the
clocks from the left/right PLL and aligns the incoming data on each
channel.
The synchronizer circuit is a 1-bit wide by 6-bit deep FIFO buffer that
compensates for any phase difference between the DPA clock and the
data realignment block. If necessary, the data realignment circuit inserts
a single bit of latency in the serial bit stream to align to the word
boundary. The deserializer includes shift registers and parallel load
registers, and sends a maximum of 10 bits to the internal logic. The data
path in the Stratix III receiver is clocked by either a dffioclk signal or
the DPA recovered clock. The deserialization factor can be statically set to
4, 6, 7, 8, or 10 by using the Quartus II software. The left/right PLLs
(PLL_Lx/PLL_Rx) generate the load enable signal, which is derived from
the deserialization factor setting.
High-Speed Differential I/O Interfaces and DPA in Stratix III Devices
Figure 9–5
shows the block of the Stratix III receiver.
Stratix III Device Handbook, Volume 1
9–7