EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 379

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Figure 11–7. FPP Configuration Timing Waveform With Decompression or Design Security Feature Enabled
Notes
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Altera Corporation
November 2007
(4)
(3)
CONF_DONE
DATA[7..0]
INIT_DONE
You should use this timing waveform when the decompression and/or design security features are used.
The beginning of this waveform shows the device in user-mode. In user-mode, nCONFIG, nSTATUS, and
CONF_DONE are at logic high levels. When nCONFIG is pulled low, a reconfiguration cycle begins.
Upon power-up, the Stratix III device holds nSTATUS low for the time of the POR delay.
Upon power-up, before and during configuration, CONF_DONE is low.
You should not leave DCLK floating after configuration. You should drive it high or low, whichever is more
convenient.
DATA[7..0] are available as user I/O pins after configuration. The state of these pins depends on the dual-purpose
pin settings.
If needed, you can pause DCLK by holding it low. When DCLK restarts, the external host must provide data on the
DATA[7..0] pins prior to sending the first DCLK rising edge.
nSTATUS
nCONFIG
(1),
User I/O
DCLK
Figure
(2)
11–7:
t
t
CFG
CF2CD
t
CF2ST1
t
CF2ST0
t
CF2CK
t
ST2CK
t
STATUS
t
High-Z
DSU
1
2
Byte 0
t
DH
3
4
1
t
CH
2
t
Byte 1
CLK
t
t
CL
DH
3
4
(6)
(6)
Byte 2
1
Stratix III Device Handbook, Volume 1
Byte n
Configuring Stratix III Devices
4
t
CD2UM
(5)
(5)
User Mode
User Mode
11–19