EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 236

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Stratix III I/O Structure
7–18
Stratix III Device Handbook, Volume 1
f
Stratix III devices have the following dedicated circuitry for high-speed
differential I/O support:
■
■
■
■
■
■
■
For more information about DPA support, refer to the
Differential I/O Interfaces with DPA in Stratix III Devices
1 of the Stratix III Device Handbook.
Programmable Current Strength
The output buffer for each Stratix III device I/O pin has a programmable
current-strength control for certain I/O standards. You can use
programmable current strength to mitigate the effects of high signal
attenuation due to a long transmission line or a legacy backplane. The
LVTTL, LVCMOS, SSTL, and HSTL standards have several levels of
current strength that you can control. Information about programmable
current strength is shown in
3.3-V LVTTL
3.3-V LVCMOS
3.0-V LVTTL
3.0-V LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVTTL/LVCMOS
1.2-V LVTTL/LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
SSTL-15 Class I
Table 7–4. Programmable Current Strength (Part 1 of 2)
Differential I/O buffer
Transmitter serializer
Receiver deserializer
Data realignment
Dynamic phase aligner (DPA)
Synchronizer (FIFO buffer)
Phase-locked loops (PLLs)
I/O Standard
I
OH
/ I
Column I/O Pins
Setting (mA) for
12, 10, 8, 6, 4, 2
12, 10, 8, 6, 4, 2
OL
12, 10, 8, 6, 4
12, 10, 8, 6, 4
Table
16, 12, 8, 4
16, 12, 8, 4
16, 12, 8, 4
16, 12, 8, 4
16, 12, 8, 4
Current Strength
8, 6, 4, 2
12, 10, 8
16, 8
16
7–4.
I
OH
/ I
Setting (mA) for
OL
12, 10, 8, 6, 4
chapter in volume
Row I/O Pins
High-Speed
Note (1)
Altera Corporation
Current Strength
8, 6, 4, 2
8, 6, 4, 2
12, 8, 4
12, 8, 4
12, 8, 4
8, 6, 4
November 2007
12, 8
16, 8
8, 4
8, 4
4, 2
16