EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 784

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

I/O Timing
1–272
Stratix III Device Handbook, Volume 2
DIFFERENTIAL
2.5-V SSTL
CLASS I
DIFFERENTIAL
2.5-V SSTL
CLASS II
RCLK input adder
RCLK PLL input adder
RCLK output adder
RCLK PLL output adder
RCLK input adder
RCLK PLL input adder
Table 1–112. EP3SE50 Row Pins Output Timing Parameters (Part 4 of 4)
Table 1–113. EP3SE50 Column Pin Delay Adders for Regional Clock
Table 1–114. EP3SE50 Row Pin Delay Adders for Regional Clock
I/O Standard
Parameter
Parameter
Strength
Current
12mA
16mA
Industrial Commercial V
Industrial Commercial V
—
—
Table 1–113
values that should be added to GCLK values. These adder values are
used to determine I/O timing when I/O pin is driven using regional
clock. This applies for all I/O standards supported by Stratix III devices.
Table 1–113
Regional Clock in Stratix III devices.
—
—
—
—
Table 1–114
Regional Clock in Stratix III devices.
GCLK
GCLK
GCLK
GCLK
Clock
PLL
PLL
Fast Model
Fast Model
Parameter
-0.004
1.744
1.885
1.889
0.014
1.75
and
specifies EP3SE50 Column Pin delay adders when using the
specifies EP3SE50 Row Pin delay adders when using the
t
t
t
t
CO
CO
CO
CO
Table 1–114
Industrial Commercial
CCL
CCL
2.653
2.659
2.861
2.869
0.093
0.076
—
—
—
—
-2
-2
=1.1V V
=1.1V V
Fast Model
show EP3SE50 regional clock (RCLK) adder
CCL
CCL
2.925
2.912
3.162
3.149
0.155
0.155
2.670
1.510
2.666
1.506
-3
=1.1V V
-3
=1.1V V
CCL
CCL
3.194
3.191
V
4.344 4.877 5.174 5.023 5.181
2.486 2.806 2.887 2.846 2.828
4.337 4.869 5.166 5.015 5.173
2.479 2.798 2.879 2.838 2.820
1.1V
3.482
0.243
0.246
3.45
-4
CCL
=1.1V V
-2
-4
=1.1V V
=
V
1.1V
CCL
-3
CCL
Altera Corporation
=
3.053
3.047
CCL
3.319
3.286
0.201
0.202
=1.1V V
November 2007
V
=1.1V V
1.1V
CCL
-4
-4L
=
-4L
V
1.1V
CCL
CCL
2.887
2.884
CCL
3.277
3.248
0.422
0.419
=0.9V
=
-4L
=0.9V
V
0.9V
CCL
=
Units
ns
ns
Units
ns
ns
ns
ns
Units
ns
ns
ns
ns